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Trace: • Software Systems and Middleware • Modern Processors: Cache, Pipeline, Superscalar, Branch Prediction, Hyperthreading • Validation Approaches • Autonomy Software Stacks • Instruction Execution Process • Register Set • Sources of Instability • Instruction Set of x64 - Essentials • Fundamentals of Data Encoding, Big Endian, Little Endian • DMA

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en:multiasm:papc:chapter_6_3 [2026/04/01 14:03] – [YMM registers] ktokarzen:multiasm:papc:chapter_6_3 [2026/04/01 14:03] (current) – [ZMM registers] ktokarz
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 The YMM registers are the 256-bit extension to the XMM registers. They are introduced to implement the AVX set of instructions. Additionally, in 64-bit processors, the number of available YMM registers was increased to 16. The YMM registers are the 256-bit extension to the XMM registers. They are introduced to implement the AVX set of instructions. Additionally, in 64-bit processors, the number of available YMM registers was increased to 16.
 ===== ZMM registers ===== ===== ZMM registers =====
-ZMM registers are the further extension of XMM registers to 512 bits. In 64-bit machines, 32 of such registers are available (figure {{ref>zmmregs}}). +ZMM registers are the further extension of XMM registers to 512 bits. In 64-bit machines, 32 of such registers are available.
- +
-<figure zmmregs> +
-{{ :en:multiasm:cs:zmm_registers.png?600 |Illustration of the 512-bit ZMM registers}} +
-<caption>512-bit ZMM registers</caption> +
-</figure>+
 XMM are the physical lower halves of YMM, which are the lower halves of ZMM. Anything written to the XMM register appears in part of the YMM and ZMM registers as presented in figure {{ref>xyzmmregs}} XMM are the physical lower halves of YMM, which are the lower halves of ZMM. Anything written to the XMM register appears in part of the YMM and ZMM registers as presented in figure {{ref>xyzmmregs}}
  
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 <caption>The relation between XMM, YMM and ZMM registers</caption> <caption>The relation between XMM, YMM and ZMM registers</caption>
 </figure> </figure>
-Together with AVX extension and ZMM registers, eight 16-bit opmask registers were introduced to x64 processors (figure {{ref>opmaskregs}}). They can be used, e.g. to provide conditional execution or mask several elements of vectors in AVX instructions. +Together with AVX extension and ZMM registers, eight 16-bit opmask registers were introduced to x64 processors. They can be used, e.g. to provide conditional execution or mask several elements of vectors in AVX instructions.
- +
-<figure opmaskregs> +
-{{ :en:multiasm:cs:opmask_registers.png?400 |Illustration of the opmask registers}} +
-<caption>Opmask registers</caption> +
-</figure>+
  
  
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