Register Set

As x86 processors evolved, the set of available registers and their size expanded. Newer processors added more general-purpose registers, as well as new registers for the FPU and vector extensions. In this chapter, we discuss the registers available to the programmer, from the 8086 up to modern 64-bit processors.

The 8086 processor has seven general-purpose registers for data storage, data manipulation and indirect addressing. Four registers: AX, BX, CX and DX can be accessed in two 8-bit halves. The lower half has the “L” letter, and the upper half has the “H” letter in the register name instead of “X”. General-purpose registers are presented in figure 1.

They have some special functions, as listed below.

• AX - Accumulator, used for general data manipulation; some instructions work only with the accumulator.
• BX - Base register, used for indirect addressing in base addressing mode.
• CX - Counter register, used for iteration counting for loops and repeated instructions.
• DX - Data register, used as an extension of the accumulator, and for I/O address space addressing.
• SI - Source index, used for indirect index addressing of source data tables or strings.
• DI - Destination index, used for indirect index addressing of destination data tables or strings.
• BP - Base pointer, often used for accessing data on the stack without the need for the stack pointer modification.

Some registers have special purposes.

• SP - Stack pointer, used for stack manipulation, automatically handles storing and retrieving the return address of procedures while calling and returning.
• IP - Instruction pointer, points to the next instruction to be executed; sometimes called program counter.

These registers are presented in figure 2.

The 8086 processor has a register containing bits that inform the software about the state of the ALU and the result of the last arithmetic or logic operation, and that control the behaviour of the CPU. It is called the Flags register, and is shown in figure 3.

The meaning of informational flags is as follows:

• CF - Carry flag, set if an operation generates a carry or borrow; for example, if the result of an addition is larger than 16 bits. Used for unsigned arguments.
• PF - Parity flag, set if the result of an operation contains an even number of bits equal to “1”.
• AF - Auxiliary Carry flag, similar to CF but informs about the carry or borrow from the 3rd to the 4th bit. It is used for BCD calculations.
• ZF - Zero flag, set if the result of an operation is zero.
• SF - Sign flag, it is a copy of the most significant bit of the result.
• OF - Overflow flag, set if the result of an operation is too large or small to fit in the destination operand. Used for signed arguments.

Control flags allow modification of the processor's behaviour:

• TF - Trap flag, used for debugging to execute a program one instruction at a time.
• IF - Interrupt flag, if set, interrupts are enabled.
• DF - Direction flag, determines the direction of string operations. If cleared, string operations work from lower to higher addresses; if set, they operate from higher to lower addresses.

The 8086, being a 16-bit processor, can address memory only in real mode (please refer to the section “Segmented addressing in real mode”). It has four segment registers:

• CS - Code segment register, used together with IP to access the instruction in the code segment.
• DS - Data segment register, used to access the default data segment.
• ES - Extra segment register, used to access an additional data segment.
• SS - Stack segment register, used together with SP or BP to access elements on the stack.

Segment registers are shown in figure 4.

Starting from the 80386 processor, the general-purpose registers, stack pointer, instruction pointer, and flags register were extended to 32 bits. Intel added an extra 16 bits to each of them, leaving the possibility to access the lower half as in previous models. For example, an accumulator can be accessed as 32-bit EAX, 16-bit AX, and 8-bit AH and AL. The resulting register set is shown in figure 5.

Similarly, the IP and flags registers were extended to 32-bit size (figure 6). Additional bits in the Eflags register are primarily used to support the virtual memory mechanism and memory protection. They are used mainly by the operating system, so we will not focus on the details here.

In 32-bit machines, two additional segment registers were added: FS and GS (figure 7). It is worth noting that all segment registers are still 16 bits long. Still, there are hidden parts, not directly available to the programmer, used to store descriptors (see the section “Segmented addressing in protected mode”).

AMD proposed the 64-bit extension to the IA-32 architecture. Registers were extended to 64 bits, and additionally, eight new general-purpose registers were added. They obtained the names R8-R15. All registers (including already known registers) can be accessed as 64-bit, 32-bit lower-order half, 16-bit lower-order quarter (word) and 8-bit lower-order byte. Registers are presented in figure 8 and in figure 9. The Eflags register is extended to 64 bits and named Rflags. The upper 32 bits of the Rflags are reserved.

The Floating Point Unit, sometimes referred to as x87, operates on eight 80-bit data registers, as shown in figure 10. They are organised as a stack, so data items are pushed into the top register. Calculations are done using the top of the stack and another register, usually the next one. Registers are named ST(0) to ST(7), where ST(0) is the top of the stack; register ST(7) is the bottom. The ST name is another term for ST(0). The registers contain the sign bit, exponent part, and significand part, encoded according to the IEEE 754 standard. Please refer to the section about data encoding and to the section about the FPU description for details of floating-point instructions.

There are also control and status registers in the Floating Point Unit as presented in figure 11.

The FPU instruction pointer, data pointer, and last-opcode registers work in conjunction with the main processor. The Tag register (figure 12) holds 2 bits of information about the state of each data register. It helps to manage the stack organisation of the data registers.

The Status word register contains information about the FPU's current state, including the top of the stack, exception flags, and condition codes (figure 13). The latter ones indicate the result of the last operation, similar to the flags in the RFlag register.

The Control word register (figure 14) enables or disables exceptions and controls the precision of calculations and the rounding of their results. The infinity bit is not meaningful in new processors.

MMX instructions are executed with the use of 64-bit packed data. Intel decided to map MMX registers onto the existing FPU registers. The MMX unit has 8 registers named MM0-MM7, as shown in figure 15. Because they are physically the same as FPU registers, it is not possible to mix MMX and FPU instructions freely.

SSE instructions are executed with the use of 128-bit packed data. To perform calculations, new 128-bit registers were introduced. The SSE unit has 8 registers named XMM0-XMM7. Because these registers are separate from all previous ones, there are no conflicts between SSE and other instructions.

To control the behaviour and provide information about the status of the SSE unit, the MXCSR register is implemented (see figure 16). It is a 32-bit register whose bits and functions are similar to those of the FPU unit's Control Word and Status Word registers, concatenated together.

The YMM registers are the 256-bit extension to the XMM registers. They are introduced to implement the AVX instruction set. Additionally, in 64-bit processors, the number of available YMM registers was increased to 16.

ZMM registers are an extension of the XMM registers, providing 512-bit registers. In 64-bit machines, 32 of such registers are available. XMM are the physical lower halves of YMM, which are, in turn, the lower halves of ZMM. Anything written to the XMM register appears in part of the YMM and ZMM registers as presented in figure 17

Along with the AVX extension and ZMM registers, eight 16-bit opmask registers were introduced in x64 processors. They can be used, e.g. to provide conditional execution or mask several elements of vectors in AVX instructions.

In the x64 architecture, additional registers are used for control purposes. The CR0, CR2, CR3, CR4, and CR8 registers control the processor's operating mode, virtual and protected memory mechanisms, and paging. The debug registers, named DR0 through DR7, control the debugging of the processor's operations and software. Memory type range registers MTRR can be used to map the address space used for the memory-mapped I/O as non-cacheable. Different processors have different sets of model-specific registers, MSR. There are also machine check registers MCR. They are used to control and report on processor performance and to detect and report hardware errors. Mostly, the described registers are not accessible to an application program and are controlled by the operating system, so they will not be described in this book. For more details, please refer to Intel documentation ¹⁾.