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Trace: • DMA • Fundamentals of Data Encoding, Big Endian, Little Endian • Modern Processors: Cache, Pipeline, Superscalar, Branch Prediction, Hyperthreading • Instruction Execution Process

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en:multiasm:papc:chapter_6_3 [2025/05/09 17:26] – [ZMM registers] ktokarzen:multiasm:papc:chapter_6_3 [2026/04/01 14:03] (current) – [ZMM registers] ktokarz
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 ====== Register Set ====== ====== Register Set ======
 +As x86 processors evolved, the set of available registers and their size expanded. Newer processors added more general-purpose registers, and new registers related to the FPU and vector extensions were added. In this chapter, we discuss the registers available to the programmer, from the 8086 up to modern 64-bit processors.
 ===== x86 registers ===== ===== x86 registers =====
 The 8086 processor has seven general-purpose registers for data storage, data manipulation and indirect addressing. Four registers: AX, BX, CX and DX can be accessed in two 8-bit halves. The lower half has the "L" letter, and the upper half has the "H" letter in the register name instead of "X". General-purpose registers are presented in Fig {{ref>gpregistresx86}}. The 8086 processor has seven general-purpose registers for data storage, data manipulation and indirect addressing. Four registers: AX, BX, CX and DX can be accessed in two 8-bit halves. The lower half has the "L" letter, and the upper half has the "H" letter in the register name instead of "X". General-purpose registers are presented in Fig {{ref>gpregistresx86}}.
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 <figure gpregistresx86> <figure gpregistresx86>
 {{ :en:multiasm:cs:GP_registers_x86.png?600 |Illustration of general purpose registers in x86 16-bit processor}} {{ :en:multiasm:cs:GP_registers_x86.png?600 |Illustration of general purpose registers in x86 16-bit processor}}
-<caption>General purpose registers in 16-bit 8086 processor</caption>+<caption> General-purpose registers in 16-bit 8086 processor</caption>
 </figure> </figure>
  
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 <figure spregistresx86> <figure spregistresx86>
-{{ :en:multiasm:cs:special_registers_x86.png?600 |Illustration of stack pointer and instruction pointer registers in x86 16-bit processor}}+{{ :en:multiasm:cs:special_registers_x86.png?600 |Illustration of stack pointer and instruction pointer registers in an x86 16-bit processor}}
 <caption>Stack pointer and instruction pointer in 16-bit 8086 processor</caption> <caption>Stack pointer and instruction pointer in 16-bit 8086 processor</caption>
 </figure> </figure>
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   * CF - Carry flag, set if an operation generates a carry or borrow; for example, if the result of an addition is larger than 16 bits. Used for unsigned arguments.   * CF - Carry flag, set if an operation generates a carry or borrow; for example, if the result of an addition is larger than 16 bits. Used for unsigned arguments.
   * PF - Parity flag, set if the result of an operation contains an even number of bits equal to "1".   * PF - Parity flag, set if the result of an operation contains an even number of bits equal to "1".
-  * AF - Auxiliary Carry flag, similar to CF but informs about the carry or borrow from 3th to the 4th bit. It is used for BCD calculations.+  * AF - Auxiliary Carry flag, similar to CF but informs about the carry or borrow from the 3rd to the 4th bit. It is used for BCD calculations.
   * ZF - Zero flag, set if the result of an operation is zero.   * ZF - Zero flag, set if the result of an operation is zero.
-  * SF - Sign flag, it is a copy of the most significant bit of the result+  * SF - Sign flag, it is a copy of the most significant bit of the result.
   * OF - Overflow flag, set if the result of an operation is too large or small to fit in the destination operand. Used for signed arguments.   * OF - Overflow flag, set if the result of an operation is too large or small to fit in the destination operand. Used for signed arguments.
  
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 </figure> </figure>
 ===== XMM registers ===== ===== XMM registers =====
-SSE instructions are executed with the use of 128-bit packed data. To perform calculations, new 128-bit registers were introduced. The SSE unit has 8 registers named XMM0 - XMM7, as presented in figure {{ref>xmmregs}}. Because these registers are separate from all previous ones, there are no conflicts between SSE and other instructions.+SSE instructions are executed with the use of 128-bit packed data. To perform calculations, new 128-bit registers were introduced. The SSE unit has 8 registers named XMM0 - XMM7. Because these registers are separate from all previous ones, there are no conflicts between SSE and other instructions.
  
-<figure xmmregs> +To control the behaviour and to provide information about the status of the SSE unit, the MXCSR register is implemented (figure {{ref>mxcsrreg}}). It is a 32-bit register with bits with their functions similar to the FPU unit's Control Word and Status Word registers concatenated together.
-{{ :en:multiasm:cs:xmm_registers.png?500 |Illustration of the 128-bit XMM registers}} +
-<caption>128-bit XMM registers</caption> +
-</figure> +
- +
-To control the behaviour and to provide information about the status of the SSE unit, the MXCSR register is implemented {{ref>mxcsrreg}}. It is a 32-bit register with bits with their functions similar to the FPU unit's Control Word and Status Word registers concatenated together.+
  
 <figure mxcsrreg> <figure mxcsrreg>
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 </figure> </figure>
 ===== YMM registers ===== ===== YMM registers =====
-The YMM registers are the 256-bit extension to the XMM registers. They are introduced to implement the AVX set of instructions. Additionally, in 64-bit processors, the number of available YMM registers was increased to 16 (figure {{ref>ymmregs}}). +The YMM registers are the 256-bit extension to the XMM registers. They are introduced to implement the AVX set of instructions. Additionally, in 64-bit processors, the number of available YMM registers was increased to 16.
- +
-<figure ymmregs> +
-{{ :en:multiasm:cs:ymm_registers.png?600 |Illustration of the 256-bit YMM registers}} +
-<caption>256-bit YMM registers</caption> +
-</figure>+
 ===== ZMM registers ===== ===== ZMM registers =====
-ZMM registers are the further extension of XMM registers to 512 bits. In 64-bit machines, 32 of such registers are available (figure {{ref>zmmregs}}).+ZMM registers are the further extension of XMM registers to 512 bits. In 64-bit machines, 32 of such registers are available. 
 +XMM are the physical lower halves of YMM, which are the lower halves of ZMM. Anything written to the XMM register appears in part of the YMM and ZMM registers as presented in figure {{ref>xyzmmregs}}
  
-<figure zmmregs> +<figure xyzmmregs> 
-{{ :en:multiasm:cs:zmm_registers.png?800 |Illustration of the 512-bit ZMM registers}} +{{ :en:multiasm:cs:xyzmm_register.png?600 |Illustration of the relation between XMM, YMM and ZMM registers}} 
-<caption>512-bit ZMM registers</caption>+<caption>The relation between XMM, YMM and ZMM registers</caption>
 </figure> </figure>
 +Together with AVX extension and ZMM registers, eight 16-bit opmask registers were introduced to x64 processors. They can be used, e.g. to provide conditional execution or mask several elements of vectors in AVX instructions.
  
-Together with AVX extension and ZMM registers, eight 16-bit opmask registers were introduced to x64 processors (figure {{ref>opmaskregs}}). They can be used, e.g. to provide conditional execution or mask several elements of vectors in AVX instructions. 
  
-<figure opmaskregs> 
-{{ :en:multiasm:cs:opmask_registers.png?400 |Illustration of the opmask registers}} 
-<caption>Opmask registers</caption> 
-</figure> 
  
-XMM are the physical lower halves of YMM, which are the lower halves of ZMM. Anything written to the XMM register appears in part of the YMM and ZMM registers as presented in figure {{ref>xyzmmregs}} 
- 
-<figure xyzmmregs> 
-{{ :en:multiasm:cs:xyzmm_register.png?800 |Illustration of the relation between XMM, YMM and ZMM registers}} 
-<caption>The relation between XMM, YMM and ZMM registers</caption> 
-</figure> 
-</note> 
 ===== Additional registers ===== ===== Additional registers =====
 In the x64 architecture, there are additional registers used for control purposes. The CR0, CR2, CR3, CR4, and CR8 registers are used for controlling the operating mode of the processor, virtual and protected memory mechanisms and paging. The debug registers, named DR0 through DR7, control the debugging of the processor’s operations and software. Memory type range registers MTRR can be used to map the address space used for the memory-mapped I/O as non-cacheable. In the x64 architecture, there are additional registers used for control purposes. The CR0, CR2, CR3, CR4, and CR8 registers are used for controlling the operating mode of the processor, virtual and protected memory mechanisms and paging. The debug registers, named DR0 through DR7, control the debugging of the processor’s operations and software. Memory type range registers MTRR can be used to map the address space used for the memory-mapped I/O as non-cacheable.
 Different processors have different sets of model-specific registers, MSR. There are also machine check registers MCR. They are used to control and report on processor performance, detect and report hardware errors. Mostly, the described registers are not accessible to an application program and are controlled by the operating system, so they will not be described in this book. For more details, please refer to Intel documentation ((https://www.intel.com/content/www/us/en/content-details/851056/intel-64-and-ia-32-architectures-software-developer-s-manual-volume-1-basic-architecture.html?wapkw=253665)). Different processors have different sets of model-specific registers, MSR. There are also machine check registers MCR. They are used to control and report on processor performance, detect and report hardware errors. Mostly, the described registers are not accessible to an application program and are controlled by the operating system, so they will not be described in this book. For more details, please refer to Intel documentation ((https://www.intel.com/content/www/us/en/content-details/851056/intel-64-and-ia-32-architectures-software-developer-s-manual-volume-1-basic-architecture.html?wapkw=253665)).
en/multiasm/papc/chapter_6_3.1746800815.txt.gz · Last modified: by ktokarz
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