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en:multiasm:papc:chapter_6_3 [2026/06/22 12:00] – pczekalskien:multiasm:papc:chapter_6_3 [2026/06/22 12:00] (current) – pczekalski
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 ====== Register Set ====== ====== Register Set ======
-As x86 processors evolved, the set of available registers and their size expanded. Newer processors added more general-purpose registers, and new registers related to the FPU and vector extensions were added. In this chapter, we discuss the registers available to the programmer, from the 8086 up to modern 64-bit processors.+As x86 processors evolved, the set of available registers and their size expanded. Newer processors added more general-purpose registers and new registers for the FPU and vector extensions. In this chapter, we discuss the registers available to the programmer, from the 8086 up to modern 64-bit processors.
 ===== x86 registers ===== ===== x86 registers =====
 The 8086 processor has seven general-purpose registers for data storage, data manipulation and indirect addressing. Four registers: AX, BX, CX and DX can be accessed in two 8-bit halves. The lower half has the "L" letter, and the upper half has the "H" letter in the register name instead of "X". General-purpose registers are presented in Fig {{ref>gpregistresx86}}. The 8086 processor has seven general-purpose registers for data storage, data manipulation and indirect addressing. Four registers: AX, BX, CX and DX can be accessed in two 8-bit halves. The lower half has the "L" letter, and the upper half has the "H" letter in the register name instead of "X". General-purpose registers are presented in Fig {{ref>gpregistresx86}}.
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 </figure> </figure>
  
-The FPU instruction pointer, data pointer, and last-opcode registers are used in cooperation with the main processor. The Tag register (Fig {{ref>fputagreg}}) holds 2 bits of information about the state of each data register. It helps to manage the stack organisation of the data registers.+The FPU instruction pointer, data pointer, and last-opcode registers work in conjunction with the main processor. The Tag register (Fig {{ref>fputagreg}}) holds 2 bits of information about the state of each data register. It helps to manage the stack organisation of the data registers.
  
 <figure fputagreg> <figure fputagreg>
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 </figure> </figure>
  
-The Control Word register (Fig {{ref>fpucontrolreg}}) turns exceptions on or off and controls the precision of calculations and the rounding of their results. The infinity bit is not meaningful in new processors.+The Control Word register (Fig {{ref>fpucontrolreg}}) enables or disables exceptions and controls the precision of calculations and the rounding of their results. The infinity bit is not meaningful in new processors.
  
 <figure fpucontrolreg> <figure fpucontrolreg>
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 The YMM registers are the 256-bit extension to the XMM registers. They are introduced to implement the AVX instruction set. Additionally, in 64-bit processors, the number of available YMM registers was increased to 16. The YMM registers are the 256-bit extension to the XMM registers. They are introduced to implement the AVX instruction set. Additionally, in 64-bit processors, the number of available YMM registers was increased to 16.
 ===== ZMM registers ===== ===== ZMM registers =====
-ZMM registers are an extension of the XMM registers to 512 bits. In 64-bit machines, 32 of such registers are available.+ZMM registers are an extension of the XMM registers, providing 512-bit registers. In 64-bit machines, 32 of such registers are available.
 XMM are the physical lower halves of YMM, which are, in turn, the lower halves of ZMM. Anything written to the XMM register appears in part of the YMM and ZMM registers as presented in Fig {{ref>xyzmmregs}} XMM are the physical lower halves of YMM, which are, in turn, the lower halves of ZMM. Anything written to the XMM register appears in part of the YMM and ZMM registers as presented in Fig {{ref>xyzmmregs}}
  
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 ===== Additional registers ===== ===== Additional registers =====
-In the x64 architecture, additional registers are used for control purposes. The CR0, CR2, CR3, CR4, and CR8 registers are used to control the processor's operating mode, virtual and protected memory mechanisms, and paging. The debug registers, named DR0 through DR7, control the debugging of the processor's operations and software. Memory type range registers MTRR can be used to map the address space used for the memory-mapped I/O as non-cacheable.+In the x64 architecture, additional registers are used for control purposes. The CR0, CR2, CR3, CR4, and CR8 registers control the processor's operating mode, virtual and protected memory mechanisms, and paging. The debug registers, named DR0 through DR7, control the debugging of the processor's operations and software. Memory type range registers MTRR can be used to map the address space used for the memory-mapped I/O as non-cacheable.
 Different processors have different sets of model-specific registers, MSR. There are also machine check registers MCR. They are used to control and report on processor performance and to detect and report hardware errors. Mostly, the described registers are not accessible to an application program and are controlled by the operating system, so they will not be described in this book. For more details, please refer to Intel documentation ((https://www.intel.com/content/www/us/en/content-details/851056/intel-64-and-ia-32-architectures-software-developer-s-manual-volume-1-basic-architecture.html?wapkw=253665)). Different processors have different sets of model-specific registers, MSR. There are also machine check registers MCR. They are used to control and report on processor performance and to detect and report hardware errors. Mostly, the described registers are not accessible to an application program and are controlled by the operating system, so they will not be described in this book. For more details, please refer to Intel documentation ((https://www.intel.com/content/www/us/en/content-details/851056/intel-64-and-ia-32-architectures-software-developer-s-manual-volume-1-basic-architecture.html?wapkw=253665)).
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