Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
en:multiasm:paarm:chapter_5_2 [2026/02/27 15:28] jtokarzen:multiasm:paarm:chapter_5_2 [2026/02/27 16:26] (current) jtokarz
Line 73: Line 73:
 The Thumb instructions have multiple machine codes for this one operation.  The Thumb instructions have multiple machine codes for this one operation. 
  
-{{ :en:multiasm:paarm:thumbt1.svg?600 |}}+<figure t1> 
 +{{ :en:multiasm:paarm:thumbt1.svg?600 |T1 THUMB instruction}} 
 +<caption>T1 THUMB instruction</caption> 
 +</figure>
  
 T1 THUMB instruction D bit and Rd fields together identify the destination register. The source and destination registers can now be addressed with only 4 bits, so only 16 general-purpose registers are accessible. A smaller number of registers can be accessed in the following machine code. T1 THUMB instruction D bit and Rd fields together identify the destination register. The source and destination registers can now be addressed with only 4 bits, so only 16 general-purpose registers are accessible. A smaller number of registers can be accessed in the following machine code.
  
-{{ :en:multiasm:paarm:thumbt2.svg?600 |}}+<figure t2> 
 +{{ :en:multiasm:paarm:thumbt2.svg?600 |T2 THUMB instruction}} 
 +<caption>T2 THUMB instruction</caption> 
 +</figure>
  
 The OP bitfield specifies the shift type, and imm5 specifies the amount. The result Rd will be shifted by imm5 bits from the Rm register. Notice that only three bits are used to address the general-purpose registers – only eight registers are accessible. The OP bitfield specifies the shift type, and imm5 specifies the amount. The result Rd will be shifted by imm5 bits from the Rm register. Notice that only three bits are used to address the general-purpose registers – only eight registers are accessible.
 Finally, the last machine code for this instruction is a sixteen 16-bit-wide instruction, but the Rd and Rm fields are still 4 bits wide. This instruction provides more shift operations than the previous one, but instead of a single imm5 field specifying the shift amount, it is split into two fields: imm3 and imm2. Both parts are combined for the same purpose: to identify the shift amount. Finally, the last machine code for this instruction is a sixteen 16-bit-wide instruction, but the Rd and Rm fields are still 4 bits wide. This instruction provides more shift operations than the previous one, but instead of a single imm5 field specifying the shift amount, it is split into two fields: imm3 and imm2. Both parts are combined for the same purpose: to identify the shift amount.
  
-{{ :en:multiasm:paarm:thumbt3.svg?600 |}}+<figure t3> 
 +{{ :en:multiasm:paarm:thumbt3.svg?600 |T3 THUMB instruction}} 
 +<caption>T3 THUMB instruction</caption> 
 +</figure>
  
 Different machine codes for the T32 instructions allow you to choose the most suitable one, but the code must be consistent with a single machine code type. Switching between machine code types in the processor is still possible, but compiling code that uses multiple machine codes will be even more complicated than learning assembler.  Different machine codes for the T32 instructions allow you to choose the most suitable one, but the code must be consistent with a single machine code type. Switching between machine code types in the processor is still possible, but compiling code that uses multiple machine codes will be even more complicated than learning assembler. 
en/multiasm/paarm/chapter_5_2.1772198939.txt.gz · Last modified: by jtokarz
CC Attribution-Share Alike 4.0 International
www.chimeric.de Valid CSS Driven by DokuWiki do yourself a favour and use a real browser - get firefox!! Recent changes RSS feed Valid XHTML 1.0