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--- en:multiasm:cs:chapter_3_8 [2025/12/05 11:59] – [Instruction Execution Process] ktokarz
+++ en:multiasm:cs:chapter_3_8 [2026/04/01 14:00] (current) – [Instruction Execution Process] ktokarz
@@ Line 1: / Line 1: @@
 ===== Instruction Execution Process ======
-As we already mentioned, instructions are executed by the processor in a few steps. You can find in the literature descriptions that there are three, four, or five stages of instruction execution. Everything depends on the level of detail one considers. The three-stage description says that there are fetch, decode and execute steps. The four-stage model says that there are fetch, decode, data read and execute steps. The five-stage version adds another final step for writing the result back and sometimes reverses the steps of data read and execution.
+As we already mentioned, instructions are executed by the processor in a few steps. The literature describes three((https://www.geeksforgeeks.org/computer-organization-architecture/different-instruction-cycles/)), four((https://www.lenovo.com/us/en/glossary/machine-cycle/)), or five((https://www.codecademy.com/article/the-instruction-cycle)) stages of instruction execution. Everything depends on the level of detail one considers. The three-stage description says that there are fetch, decode and execute steps. The four-stage model says that there are fetch, decode, data read and execute steps, or fetch, decode, execute and store steps. The five-stage version adds both data read and write the result back, and sometimes reverses the order of data read and execution.
 It is worth remembering that even a simple fetch step can be divided into a set of smaller actions which must be performed by the processor. The real execution of instructions depends on the processor's architecture, implementation and complexity. Considering the five-stage model, we can describe the general stages of instruction execution:
@@ Line 21: / Line 21: @@
   - Writing back the result:
     * The processor writes the result of calculations into the register or memory.
+The 5-stage instruction execution is illustrated in figure {{ref>instr5stage}}
+<figure instr5stage>
+{{ :en:multiasm:cs:instruction_5_stages.png?700 |The five-stage instruction execution process}}
+<caption>The five stage instruction execution process</caption>
+</figure>
 ===== Instruction encoding =====
-From the perspective of the processor, instructions are binary codes, unambiguously determining the activities that the processor is to perform. Instructions can be encoded using a fixed or variable number of bits.
+From the processor's perspective, instructions are binary codes that unambiguously determine the activities the processor is to perform. Instructions can be encoded using a fixed or variable number of bits.
-A fixed number of bits makes the construction of the instruction decoder simpler because the choice of some specific behaviour or function of the execution unit is encoded with the bits, which are always at the same position in the instruction. On the opposite side, if the designer plans to expand the instruction set with new instructions in the future, there must be some spare bits in the instruction word reserved for future use. It makes the code of the program larger than required. Fixed lengths of instructions are often implemented in RISC machines. For example, in the ARM architecture, instructions have 32 bits. In AVR, instructions are encoded using 16 bits.
+A fixed number of bits makes the construction of the instruction decoder simpler because the choice of some specific behaviour or function of the execution unit is encoded with the bits, which are always at the same position in the instruction. On the opposite side, if the designer plans to expand the instruction set with new instructions in the future, there must be some spare bits in the instruction word reserved for future use. It makes the program's code unnecessarily large. Fixed-length instructions are often implemented on RISC machines. For example, in the ARM architecture, instructions have 32 bits. In AVR, instructions are encoded using 16 bits.
-A variable number of bits makes the instruction decoder more complex. Based on the content of the first part of the instruction (usually a byte), it must be able to decide what is the length of the whole instruction. In such an approach, instructions can be as short as one byte or much longer. An example of a processor with variable instruction length is the 8086 and all further processors from the x86 and x64 families. Here, the instructions, including all possible constant arguments, can have even 15 bytes.
+A variable number of bits makes the instruction decoder more complex. Based on the content of the first part of the instruction (usually a byte), it must be able to decide what is the length of the whole instruction. In such an approach, instructions can be as short as one byte or much longer. An example of a processor with variable instruction length is the 8086, and all subsequent processors in the x86 and x64 families. Here, the instructions, including all possible constant arguments, can be as long as 15 bytes.
 <note info>
 Although in the computer world information is very often encoded in bytes or multiples of bytes, there are processors with instructions encoded in other numbers of bits. Examples include PIC microcontrollers with an instruction length of 13 or 14 bits.</note>

en/multiasm/cs/chapter_3_8.1764928797.txt.gz · Last modified: 2025/12/05 11:59 by ktokarz