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| en:multiasm:cs:chapter_3_7 [2026/06/21 14:54] – pczekalski | en:multiasm:cs:chapter_3_7 [2026/06/22 17:20] (current) – pczekalski |
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| ===== Addressing of I/O devices ===== | ===== Addressing of I/O devices ===== |
| From the assembler programmer's perspective, the peripheral device is represented as a set of registers available in the I/O address space. Registers of peripherals are used to control their behaviour, including mode of operation, parameters, configuration, transmission speed, etc. Registers are also data exchange points where the processor can store data to be transmitted to the user or an external computer, or read data from the user or another system. | From the assembler programmer's perspective, the peripheral device is represented as a set of registers available in the I/O address space. Peripheral registers are used to control their behaviour, including mode of operation, parameters, configuration, transmission speed, etc. Registers are also data exchange points where the processor can store data to be transmitted to the user or an external computer, or read data from the user or another system. |
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| The size of the I/O address space is usually smaller than the size of the program or data address space. The method of accessing peripherals depends on the processor's design. We can find two methods of I/O addressing implementation: separate or memory-mapped I/O. | The size of the I/O address space is usually smaller than the size of the program or data address space. The method of accessing peripherals depends on the processor's design. We can find two methods of I/O addressing: separate and memory-mapped I/O. |
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| ===== Separate I/O address space ===== | ===== Separate I/O address space ===== |
| A separate I/O address space is accessed independently of the program or data memory. In the processor, it is implemented with separate control bus lines for reading or writing I/O devices. Separate control lines usually mean that the processor also implements different instructions to access memory and I/O devices. It also means that the chosen peripheral and the byte in memory can have the same address, and only the instruction type distinguishes the final destination of the address. | A separate I/O address space is accessed independently of the program or data memory. In the processor, it is implemented with separate control bus lines for reading or writing I/O devices. Separate control lines usually mean that the processor also implements different instructions to access memory and I/O devices. It also means that the chosen peripheral and the byte in memory can have the same address, and only the instruction type distinguishes the final destination of the address. |
| A separate I/O address space is shown schematically in Fig. {{ref>separateio}}. Reading data from memory is activated by the #MEMRD signal; writing is activated by the #MEMWR signal. If the processor needs to read or write the peripheral device's register, it uses #IORD or #IOWR, respectively. | A separate I/O address space is shown schematically in figure {{ref>separateio}}. Reading data from memory is activated by the #MEMRD signal; the #MEMWR signal activates writing. If the processor needs to read or write the peripheral device's register, it uses #IORD or #IOWR, respectively. |
| <note info> | <note info> |
| The "#" symbol before a signal name means that the active signal on the line is a LOW state, while idle is a HIGH state. | The "#" symbol before a signal name means that the active signal on the line is a LOW state, while idle is a HIGH state. |
| ===== Memory-mapped I/O address space ===== | ===== Memory-mapped I/O address space ===== |
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| In this approach, the processor doesn't implement separate control signals to access the peripherals. It uses a #RD signal to read the data from and a #WR signal to write the data to a common address space. It also doesn't have separate instructions for accessing registers in the I/O address space. Every such register is visible like any other memory location. It means that the software is solely responsible for distinguishing I/O registers from data in memory. | In this approach, the processor doesn't implement separate control signals to access the peripherals. It uses a #RD signal to read the data from and a #WR signal to write the data to a common address space. It also doesn't have separate instructions for accessing registers in the I/O address space. Every such register is visible like any other memory location. It means the software is solely responsible for distinguishing I/O registers from memory data. |
| Memory-mapped I/O address space is shown schematically in Fig {{ref>memorymappedio}}. | Memory-mapped I/O address space is shown schematically in figure {{ref>memorymappedio}}. |
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| <figure memorymappedio> | <figure memorymappedio> |
