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en:multiasm:piot:chapter_4_6 [2024/09/27 23:20] – created pczekalskien:multiasm:piot:chapter_4_6 [2026/03/01 19:55] (current) – ktokarz
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-====== Instruction encoding ======+====== Instruction Encoding ====== 
 + 
 +Assembler instructions have a specific format that defines the operation and its arguments. The instruction format can vary depending on the processor architecture. Instruction encoding involves representing operations in binary form. Instructions can vary in length, from one to several bytes. Encoding instructions is crucial for the processor's efficient execution of a program. 
 + 
 +Instructions for AVR microcontrollers involve converting assembler instructions into machine code that the processor can execute directly. Each assembler instruction is represented by a specific set of bits that define the operation and its operands. 
 + 
 +**Instruction Format:** 
 +  * AVR instructions are encoded in 16-bit or 32-bit machine words. 
 +  * 16-bit instructions are most commonly used, but some more complex instructions may require 32-bit encoding. 
 + 
 +**Bit Allocation:** 
 +  * Opcode: Specifies the type of operation (e.g., addition, subtraction, shift). 
 +  * Registers: Specification of source and destination registers. 
 +  * Constants: Immediate values used in instructions. 
 +  * Addresses: Memory addresses used in load and store instructions. 
 + 
 +**Opcodes:** 
 + 
 +Opcodes are fixed bit patterns that identify the instruction type.   
 +AVR has no single universal format – different commands use different bit counts.   
 +Below are typical instruction formats. 
 + 
 +---- 
 + 
 +===== AVR Instruction Formats ===== 
 + 
 + 
 +**1. Register–Register ALU Operations (16 bit)** 
 + 
 +**Commands:** ADD, ADC, SUB, SBC, AND, OR, EOR, CP, CPC, MOV 
 + 
 +^ Format      ^ Bit Pattern            ^ Description                     ^ 
 +| ALU Rd, Rr  | 0000 11rd dddd rrrr    | Rd = destination, Rr = source   | 
 + 
 +** Explanation ** 
 + 
 +In the format **0000 11rd dddd rrrr**, bits for Rr and Rd are separated because: 
 + 
 +  * the instruction format follows opcode layout   
 +  * opcode = first 6 bits   
 +  * one source bit **r** sits near the opcode   
 +  * remaining **rrrr** are at the end   
 +  * all **ddddd** for Rd sit in the middle   
 + 
 +This matches AVR decoding logic. 
 + 
 + 
 +---- 
 + 
 + 
 +** 2. Immediate ALU Operations (16 bit) ** 
 + 
 +**Commands:** LDI, SUBI, CPI, ORI, ANDI 
 + 
 +^ Format       ^ Bit Pattern             ^ Description                  ^ 
 +| LDI Rd, K    | 1110 KKKK dddd KKKK     | 8‑bit immediate (R16–R31)    | 
 +| SUBI Rd, K   | 0101 KKKK dddd KKKK     | Subtract immediate           | 
 +| CPI Rd, K    | 0011 KKKK dddd KKKK     | Compare immediate            | 
 + 
 +** Explanation of 1110 KKKK dddd KKKK ** 
 + 
 +The instruction **LDI Rd, K** loads an 8‑bit constant into Rd (only R16–R31). 
 + 
 +Format: 
 + 
 +1110 KKKK dddd KKKK 
 + 
 +Why is immediate **K** split? 
 + 
 +  * opcode uses first 4 bits → **1110** 
 +  * AVR must place 8‑bit immediate + 4 register bits inside 12 bits 
 +  * upper 4 bits → first **KKKK** 
 +  * lower 4 bits → second **KKKK** 
 + 
 +Why is **dddd** in the middle? 
 + 
 +  * registers R16–R31 have MSB=1   
 +  * only lower 4 bits need encoding   
 + 
 + 
 +---- 
 + 
 + 
 +** 3. Single Register Operations (16 bit) ** 
 + 
 +**Commands:** INC, DEC, COM, NEG, LSR, ROR, ASR, SWAP 
 + 
 +^ Instruction  ^ Bit Pattern            ^ 
 +| INC Rd       | 1001 010d dddd 0011   | 
 +| DEC Rd       | 1001 010d dddd 1010   | 
 + 
 +---- 
 + 
 +** 4. Branch Instructions (16 bit) ** 
 + 
 +**Commands:** RJMP, RCALL, BREQ, BRNE, BRGE, BRLT, etc. 
 + 
 +^ Format   ^ Bit Pattern              ^ Description           ^ 
 +| RJMP k   | 1100 kkkk kkkk kkkk      | 12‑bit relative jump  | 
 +| RCALL k  | 1101 kkkk kkkk kkkk      | 12‑bit relative call  | 
 +| BRxx k   | 1111 00kk kkkk ksss      | Conditional branch    | 
 + 
 +---- 
 + 
 +** 5. Absolute Jumps and Calls (32 bit) ** 
 + 
 +**Commands:** JMP, CALL 
 + 
 +^ Format  ^ Bit Pattern                                   ^ Description        ^ 
 +| JMP k   | 1001 010k kkkk 110k + kkkk kkkk kkkk kkkk      | 22‑bit address     | 
 +| CALL k  | 1001 010k kkkk 111k + kkkk kkkk kkkk kkkk      | 22‑bit address     | 
 + 
 +---- 
 + 
 +** 6. Load/Store with Register Indirect (16 bit) ** 
 + 
 +**Commands:** LD, ST with X, Y, Z 
 + 
 +^ Format       ^ Bit Pattern             ^ Description          ^ 
 +| LD Rd, X     | 1001 000d dddd 1100     | Load from X          | 
 +| ST X, Rr     | 1001 001r rrrr 1100     | Store to X           | 
 +| LD Rd, Y+    | 1001 000d dddd 1001     | Post‑increment       | 
 +| LD Rd, -Z    | 1001 000d dddd 0010     | Pre‑decrement        | 
 + 
 +---- 
 + 
 +** 7. Load/Store with Displacement (16 bit) ** 
 + 
 +**Commands:** LDD, STD 
 + 
 +^ Format         ^ Bit Pattern           ^ 
 +| LDD Rd, Y+q    | 10q0 qq0d dddd 1qqq   | 
 +| STD Y+q, Rr    | 10q0 qq1r rrrr 1qqq   | 
 + 
 +---- 
 + 
 +**8. I/O Register Access (16 bit) ** 
 + 
 +**Commands:** IN, OUT 
 + 
 +^ Format      ^ Bit Pattern            ^ 
 +| IN Rd, A    | 1011 0AAd dddd AAAA   | 
 +| OUT A, Rr   | 1011 1AAr rrrr AAAA   | 
 + 
 +---- 
 + 
 +**9. Bit Manipulation (16 bit) ** 
 + 
 +**Commands:** SBI, CBI, SBIC, SBIS, BST, BLD 
 + 
 +^ Format      ^ Bit Pattern            ^ 
 +| SBI A, b    | 1001 1010 AAAA Abbb   | 
 +| CBI A, b    | 1001 1000 AAAA Abbb   | 
 +| SBIC A, b   | 1001 1011 AAAA Abbb   | 
 + 
 +---- 
 + 
 +**10. Program Memory Access (LPM, ELPM, SPM) ** 
 + 
 +^ Instruction   ^ Bit Pattern            ^ Description               ^ 
 +| LPM Rd, Z     | 1001 000d dddd 0100    | Load from program memory  | 
 +| ELPM Rd, Z    | 1001 000d dddd 0110    | Extended load (RAMPZ)     | 
 +| SPM           | 1001 0101 1111 1000    | Store to program memory   | 
 + 
 +---- 
 + 
 +** 11. Stack Operations (16 bit) ** 
 + 
 +**Commands:** PUSH, POP 
 + 
 +^ Instruction  ^ Bit Pattern             ^ 
 +| PUSH Rr      | 1001 001r rrrr 1111     | 
 +| POP Rd       | 1001 000d dddd 1111     | 
 + 
 +---- 
 + 
 +**12. Control Instructions (16 bit) ** 
 + 
 +**Commands:** NOP, SLEEP, WDR, BREAK 
 + 
 +^ Instruction  ^ Bit Pattern             ^ 
 +| NOP          | 0000 0000 0000 0000     | 
 +| SLEEP        | 1001 0101 1000 1000     | 
 +| WDR          | 1001 0101 1010 1000     | 
 + 
 +---- 
 + 
 +**Notes ** 
 + 
 +  * **d** = destination register bits   
 +  * **r** = source register bits   
 +  * **K** = immediate value bits   
 +  * **A** = I/O address bits   
 +  * **k** = jump offset or absolute address bits   
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