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en:multiasm:piot:chapter_4_5 [2026/03/01 19:33] – [Extended Indirect Program Memory Addressing] ktokarzen:multiasm:piot:chapter_4_5 [2026/04/01 14:21] (current) – ktokarz
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 ====== Addressing Modes ====== ====== Addressing Modes ======
  
-Addressing modes define how the processor accesses data. There are 15 different addressing modes, such as: Direct Addressing, Indirect Addressing, Indirect with Displacement, Immediate Addressing, Register Addressing, Relative Addressing, Indirect I/O Addressing, and Stack Addressing. +Addressing modes define how the processor accesses data and the target address of a jump. There are more than a dozen different addressing modes, such as: Direct Addressing, Indirect Addressing, Indirect with Displacement, Immediate Addressing, Register Addressing, Relative Addressing, Indirect I/O Addressing, and others. In this section, we first present the data addressing and later addressing used in flow control instructions.
- +
-Details on addressing modes are presented in Fig. {{ref>avr_addr_1}},{{ref>avr_addr_2}},{{ref>avr_addr_3}},{{ref>avr_addr_4}},{{ref>avr_addr_5}},{{ref>avr_addr_6}},{{ref>avr_addr_7}},{{ref>avr_addr_8}},{{ref>avr_addr_9}},{{ref>avr_addr_10}},{{ref>avr_addr_11}},{{ref>avr_addr_12}},{{ref>avr_addr_13}},{{ref>avr_addr_14}} and {{ref>avr_addr_15}}:+
  
 =====Direct Single Register Addressing===== =====Direct Single Register Addressing=====
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 =====Data Indirect Addressing===== =====Data Indirect Addressing=====
-Indirect addressing uses the content of an index register as a pointer to memory. As shown in Fig {{ref>avr_addr_5}}, the operand address is the contents of the X-, Y-, or Z-pointer. Please note that X is formed with concatenated registers R27 and R26, Y is built with R29 and R28, and Z with R31 and R30. In AVR devices without SRAM, Data Indirect Addressing is called Register Indirect Addressing.+Indirect addressing uses the content of an index register as a pointer to memory. As shown in Fig {{ref>avr_addr_5}}, the operand address is the contents of the X, Y, or Z pointer. Please note that X is formed with concatenated registers R27 and R26, Y is built with R29 and R28, and Z with R31 and R30. In AVR devices without SRAM, Data Indirect Addressing is called Register Indirect Addressing.
 An example of the instruction is load data from memory addressed with an X pointer. An example of the instruction is load data from memory addressed with an X pointer.
 <code asm> <code asm>
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 =====Program Memory Constant Addressing===== =====Program Memory Constant Addressing=====
-With this addressing mode, it is possible to read the byte from the program memory. As shown in Fig {{ref>avr_addr_9}}, the byte address in program memory is determined by the value stored in the Z-pointer.+With this addressing mode, it is possible to read the byte from the program memory. As shown in Fig {{ref>avr_addr_9}}, the byte address in program memory is determined by the value stored in the Z pointer.
  
 The upper 15 bits (Most Significant bits - MSbs) select the word address (each word contains 2 bytes). The upper 15 bits (Most Significant bits - MSbs) select the word address (each word contains 2 bytes).
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 =====Program Memory Addressing with Post-increment===== =====Program Memory Addressing with Post-increment=====
-<todo @pczekalski>Continue figures formatting here</todo> 
 Program memory can be addressed with post-increment mode. In this mode, the Z pointer is automatically incremented after reading. Program memory can be addressed with post-increment mode. In this mode, the Z pointer is automatically incremented after reading.
 As shown in Fing {{ref>avr_addr_10}}, the Z-pointer contents specify a constant byte address. The 15 MSbs select the word address. The LSb selects the low byte if cleared (LSb == 0) or the high byte if set (LSb == 1).  As shown in Fing {{ref>avr_addr_10}}, the Z-pointer contents specify a constant byte address. The 15 MSbs select the word address. The LSb selects the low byte if cleared (LSb == 0) or the high byte if set (LSb == 1). 
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 As visible in Fig {{ref>avr_addr_11}}, for the **spm** instruction, the LSb must be 0, because **spm** works on whole words. The Z-pointer is incremented by 2 after the operation. The Z-pointer contents specify a constant byte address before incrementing. The 15 MSbs select the word address, and the LSb should be left cleared. As visible in Fig {{ref>avr_addr_11}}, for the **spm** instruction, the LSb must be 0, because **spm** works on whole words. The Z-pointer is incremented by 2 after the operation. The Z-pointer contents specify a constant byte address before incrementing. The 15 MSbs select the word address, and the LSb should be left cleared.
  
-<todo @mfojcik>Marcin, tu mam wątpliwości co do nazwy tego rozdziału - to addressing mode? KT odpowiadam - według dokmentacji AVR tak</todo> 
 <figure avr_addr_11> <figure avr_addr_11>
 {{ :en:multiasm:piot:ad11.png?600 |Store Program Memory}} {{ :en:multiasm:piot:ad11.png?600 |Store Program Memory}}
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 </figure> </figure>
  
-<todo @mfojcik> "immediate" -> "following immediately the instruction word"? KT - opisałem to dokładniej, Janek zmodyfikuje rysunek bo jest trochę nielogiczny</todo>+
  
 =====Indirect Program Memory Addressing===== =====Indirect Program Memory Addressing=====
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 =====Extended Indirect Program Memory Addressing===== =====Extended Indirect Program Memory Addressing=====
-For versions of AVR microcontrollers with bigger program memory than 128 kB, additional bits used to extend the address are stored in the EIND register. Program execution continues at the address contained by the Z-register and the EIND-register (i.e., the PC is loaded with the contents of the EIND and Z-register) as shown in fig {{ref>avr_addr_14}}.+For versions of AVR microcontrollers with bigger program memory than 128 kB, additional bits used to extend the address are stored in the EIND register. Program execution continues at the address contained by the Z register and the EIND register (i.e., the PC is loaded with the contents of the EIND and Z register) as shown in fig {{ref>avr_addr_14}}.
  
 <figure avr_addr_14> <figure avr_addr_14>
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 =====Relative Program Memory Addressing===== =====Relative Program Memory Addressing=====
 +If the target address is within the range of -2048 to 2047 from the current address, the shorter relative control transfer instructions can be used. 
 +As shown in fig {{ref>avr_addr_15}}, program execution continues at the address PC + k + 1. The constant //k// does not represent the absolute address, so it must be calculated as a difference between the current address plus 1 and the target address. It is treated as a signed value, so the target address can be higher or lower than the current one. 
 +<code asm> 
 +RJMP target 
 +</code>
 <figure avr_addr_15> <figure avr_addr_15>
 {{ :en:multiasm:piot:ad15.png?600 |Relative Program Memory Addressing}} {{ :en:multiasm:piot:ad15.png?600 |Relative Program Memory Addressing}}
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 </figure> </figure>
  
-Program execution continues at the address PC + k + 1. The relative address k is from -2048 to 2047.+
en/multiasm/piot/chapter_4_5.1772386402.txt.gz · Last modified: by ktokarz
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