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| en:multiasm:piot:chapter_4_2 [2026/01/10 20:38] – pczekalski | en:multiasm:piot:chapter_4_2 [2026/03/01 17:41] (current) – [Microcontroller Architecture – Component Overview] ktokarz | ||
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| ====== Specific Elements of AVR Architecture ====== | ====== Specific Elements of AVR Architecture ====== | ||
| - | AVR is an extension of the idea presented in Vegard Wollan and Alf-Egil Bogen' | + | AVR is an extension of the idea presented in Vegard Wollan and Alf-Egil Bogen' |
| + | ==== AVR Architecture ==== | ||
| AVR architecture (Fig. {{ref> | AVR architecture (Fig. {{ref> | ||
| * RISC Architecture: | * RISC Architecture: | ||
| Line 15: | Line 16: | ||
| <figure avr_architecture> | <figure avr_architecture> | ||
| - | {{: | + | {{ : |
| - | < | + | < |
| </ | </ | ||
| + | ==== AVR Components Overview ==== | ||
| - | Other Architectures: | + | * Interrupt Unit - Handles asynchronous events by temporarily halting the main program flow to execute interrupt service routines. |
| - | PIC | + | * SPI Unit - Implements the Serial Peripheral Interface protocol for high-speed synchronous data exchange with external devices. |
| + | * Watchdog Timer - A fail-safe timer that resets the system if the software becomes unresponsive or enters an infinite loop. | ||
| + | * Analogue Comparator - Compares two analogue input voltages and outputs a digital signal based on their relative magnitude. | ||
| + | * I/O Module - Interfaces with external peripherals, | ||
| + | * Flash Program Memory - Non-volatile memory used to store the program code, retaining data even when power is lost. | ||
| + | * Instruction Register - Temporarily holds the current instruction fetched from program memory before decoding. | ||
| + | * Instruction Decoder - Translates the binary instruction into control signals that direct the operation of internal units. | ||
| + | * Control Lines - Carry control signals that coordinate data flow and operations across the microcontroller. | ||
| + | * Program Counter - Keeps track of the address of the next instruction to be executed, enabling sequential program flow. | ||
| + | * Status and Control - Stores flags and control bits that reflect the current state of the processor and influence execution. | ||
| + | * 32×8 General Purpose Register - A set of 32 registers, each 8 bits wide, used for temporary data storage and arithmetic operations. | ||
| + | * ALU (Arithmetic Logic Unit) - Performs arithmetic and logical operations on data from the general-purpose registers. | ||
| + | * Data SRAM - Volatile memory used for runtime data storage, such as variables and stack operations. | ||
| + | * EEPROM - Electrically erasable non-volatile memory for storing user data that must persist across power cycles. | ||
| + | * I/O Lines - Physical pins that connect the microcontroller to external circuits for input and output tasks. | ||
| + | * Data Bus - An 8-bit pathway that transfers data between internal components, enabling communication and processing. | ||
| + | |||
| + | |||
| + | ====Other Architectures==== | ||
| + | There are other popular microcontrollers available on the market, which are the main competitors to AVR. We depict some of them shortly. | ||
| + | |||
| + | __PIC__ | ||
| * Manufacturer: | * Manufacturer: | ||
| * Architecture: | * Architecture: | ||
| Line 28: | Line 51: | ||
| * PIC32: 32-bit microcontrollers, | * PIC32: 32-bit microcontrollers, | ||
| - | ESP8266/ESP32 | + | __ESP8266/ESP32__ |
| * Manufacturer: | * Manufacturer: | ||
| * Architecture: | * Architecture: | ||
| Line 34: | Line 57: | ||
| * ESP32: Dual-core processor, 240 MHz, 520 KB SRAM, Wi-Fi, Bluetooth, more GPIO | * ESP32: Dual-core processor, 240 MHz, 520 KB SRAM, Wi-Fi, Bluetooth, more GPIO | ||
| - | TI MSP430 | + | __TI MSP430__ |
| * Manufacturer: | * Manufacturer: | ||
| * Architecture: | * Architecture: | ||
