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en:multiasm:papc:chapter_6_6 [2026/06/22 12:25] – pczekalskien:multiasm:papc:chapter_6_6 [2026/06/22 12:47] (current) – pczekalski
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 In 64-bit mode, the CS, SS, DS and ES segment overrides are ignored. In 64-bit mode, the CS, SS, DS and ES segment overrides are ignored.
  
-The **branch hint** prefixes can appear together with conditional jump instructions. These prefixes can be used to support the branch prediction unit of the processor in determining if the branch shall be taken (0x3E) or not taken (0x2E). This function is enabled if there is no history in the branch prediction unit yet, and static branch prediction is used.+The **branch hint** prefixes can appear together with conditional jump instructions. These prefixes can be used to support the processor's branch prediction unit in determining whether the branch shall be taken (0x3E) or not taken (0x2E). This function is enabled if there is no history in the branch prediction unit yet, and static branch prediction is used.
  
-The **operand size** and **address size override** prefixes can change the default size of operands and addresses. For example, if the processor operates in 32-bit mode, using the 0x66 prefix changes the size of an operand to 16 bits, and using the 0x67 prefix changes the address encoding from 32 bits to 16 bits. To better understand the behaviour of prefixes, let us consider a simple instruction with different variants. Let's start with a 32-bit processor.+The **operand size** and **address size override** prefixes can change the default size of operands and addresses. For example, if the processor operates in 32-bit mode, using the 0x66 prefix changes an operand size to 16 bits, and using the 0x67 prefix changes the address encoding from 32 bits to 16 bits. To better understand the behaviour of prefixes, let us consider a simple instruction with different variants. Let's start with a 32-bit processor.
 <code asm> <code asm>
                           ;encoding                           ;encoding
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 </code> </code>
  
-We can notice that because the default operand size is a 32-bit doubleword, the prefix 0x66 appears in the 16-bit version (WORD PTR). It is also visible that the 8-bit version (BYTE PTR) has a different opcode (0xC6, 0x03 instead of 0xC7, 0x03). Also, the size of the argument is different.+We can see that, because the default operand size is a 32-bit doubleword, the 16-bit version (WORD PTR) uses the 0x66 prefix. It is also visible that the 8-bit version (BYTE PTR) has a different opcode (0xC6, 0x03 instead of 0xC7, 0x03). Also, the size of the argument is different.
  
-The address override prefix (0x67) appears if we change the register to a 16-bit bx.+The address-override prefix (0x67) appears when we change the register to a 16-bit bx.
 <code asm> <code asm>
                          ;encoding                          ;encoding
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 <note>We encourage you to assemble or disassemble some further instructions. You can do it with an Online x86 / x64 Assembler and Disassembler ((https://defuse.ca/online-x86-assembler.htm#disassembly)) by Taylor Hornby. Experimentation can give you valuable information on where some information is encoded in the instruction. </note> <note>We encourage you to assemble or disassemble some further instructions. You can do it with an Online x86 / x64 Assembler and Disassembler ((https://defuse.ca/online-x86-assembler.htm#disassembly)) by Taylor Hornby. Experimentation can give you valuable information on where some information is encoded in the instruction. </note>
 =====Instruction opcode===== =====Instruction opcode=====
-The instruction opcode is the mandatory field in every instruction. It encodes the main function of the operation. Expanding the processor's capabilities by adding new instructions required defining longer opcodes. The opcode can be 1, 2 or 3 bytes in length. New instructions usually contain an additional byte or two bytes at the beginning called an escape sequence. Possible opcode sequences are:+The instruction opcode is the mandatory field in every instruction. It encodes the operation's main function. Expanding the processor's capabilities by adding new instructions required defining longer opcodes. The opcode can be 1, 2 or 3 bytes in length. New instructions usually contain an additional byte or two bytes at the beginning called an escape sequence. Possible opcode sequences are:
 <code asm> <code asm>
 opcode opcode
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 vblendvpd xmm0, xmm1, xmm2, xmm3  ;0xC4, 0xE3, 0x71, 0x4B, 0xC2, 0x30  vblendvpd xmm0, xmm1, xmm2, xmm3  ;0xC4, 0xE3, 0x71, 0x4B, 0xC2, 0x30 
 </code> </code>
-The first blendvpd instruction has only two arguments; in this encoding scheme is not possible to encode more. It uses the mandatory prefix 0x66 and 0x0F, 0x38 escape sequence. The second version, vblendvpd, has four arguments. It is encoded with a three-byte VEX escape sequence 0xC4, 0xE3, 0x71.+The first blendvpd instruction has only two arguments; in this encoding scheme, it is not possible to encode more. It uses the mandatory prefixes 0x66 and 0x0F, and the escape sequence 0x38. The second version, vblendvpd, has four arguments. It is encoded with a three-byte VEX escape sequence 0xC4, 0xE3, 0x71.
  
 =====MOD R/M byte===== =====MOD R/M byte=====
-The ModR/M byte encodes the addressing mode, a register which is used as an operand in the instruction, and registers used for addressing of memory. It can also extend the opcode in some instructions. It has the fields as shown in the figure {{ref>modrm_byte}}.+The ModR/M byte encodes the addressing mode, a register which is used as an operand in the instruction, and the registers used for memory addressing. It can also extend the opcode in some instructions. It has the fields as shown in the figure {{ref>modrm_byte}}.
  
 <figure modrm_byte> <figure modrm_byte>
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   * Mod - Mode. This 2-bit field gives the register/memory mode.    * Mod - Mode. This 2-bit field gives the register/memory mode. 
   * Reg - Register. This 3-bit field specifies one of the general-purpose registers used as the operand. It can also be the opcode extension.   * Reg - Register. This 3-bit field specifies one of the general-purpose registers used as the operand. It can also be the opcode extension.
-  * R/M - Register/memory. This 3-bit field specifies the second register as the operand or combination of registers used in the calculation of the address in memory.+  * R/M - Register/memory. This 3-bit field specifies the second register as the operand, or a combination of registers, used in calculating the memory address.
  
 In x86, the Mod field specifies one of four possible memory addressing modes, and the R/M field specifies which register, or pair of registers, is used for address calculation. If the Mod field is 11 (binary), the R/M field specifies the second register in the instruction. Details are shown in table {{ref>modrm_16}} In x86, the Mod field specifies one of four possible memory addressing modes, and the R/M field specifies which register, or pair of registers, is used for address calculation. If the Mod field is 11 (binary), the R/M field specifies the second register in the instruction. Details are shown in table {{ref>modrm_16}}
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 In 32-bit mode, registers used for addressing can be specified with the SIB byte, but this is not always the case. If a single register is used (with some exceptions), it still can be encoded with the MOD R/M byte, and there is no SIB byte in the instruction.  In 32-bit mode, registers used for addressing can be specified with the SIB byte, but this is not always the case. If a single register is used (with some exceptions), it still can be encoded with the MOD R/M byte, and there is no SIB byte in the instruction. 
-In 64-bit long mode, the MOD R/M byte encoding works in a similar manner to 32-bit, with the difference that the MOD R/M byte is extended with R and B bits from the REX prefix, enabling the use of more registers in instructions.+In 64-bit long mode, the MOD R/M byte encoding works similarly to 32-bit, with the difference that the MOD R/M byte is extended with R and B bits from the REX prefix, enabling the use of more registers in instructions.
  
 <table modrm_640> <table modrm_640>
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 In the tables {{ref>SIB_index}} and {{ref>SIB_index64}}, the * means that there is no index register encoded in the instruction. It results in base-only or direct addressing. In the tables {{ref>SIB_index}} and {{ref>SIB_index64}}, the * means that there is no index register encoded in the instruction. It results in base-only or direct addressing.
  
-Let's look at some code examples, considering the 32-bit version first. In all instructions, there is a MOD R/M byte and an SIB byte. MOD R/M is identical for all instructions. REG field indicates eax register and the combination of MOD and R/M indicates that registers are specified with the SIB byte.+Let's look at some code examples, starting with the 32-bit version. In all instructions, there is a MOD R/M byte and an SIB byte. MOD R/M is identical for all instructions. REG field indicates the eax register, and the combination of MOD and R/M indicates that the registers are specified with the SIB byte.
 <code asm> <code asm>
 ;MOD R/M (second byte) is 0x04 for all instructions: ;MOD R/M (second byte) is 0x04 for all instructions:
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 </code> </code>
  
-And other examples for x64 processors. The SIB byte is extended with bits from the REX prefix. We'll start with the similar examples as shown for 32-bit machines.+And other examples for x64 processors. The SIB byte is extended with bits from the REX prefix. We'll start with similar examples as shown for 32-bit machines.
  
 <code asm> <code asm>
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 Certainly, the presented examples do not exhaust all possible situations. For a more detailed explanation, please refer to the documentation by AMD((https://docs.amd.com/v/u/en-US/40332-PUB_4.08)), Intel((https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)), OSDev wiki((https://wiki.osdev.org/X86-64)) or other interesting sources mentioned at the bottom of this section. Certainly, the presented examples do not exhaust all possible situations. For a more detailed explanation, please refer to the documentation by AMD((https://docs.amd.com/v/u/en-US/40332-PUB_4.08)), Intel((https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)), OSDev wiki((https://wiki.osdev.org/X86-64)) or other interesting sources mentioned at the bottom of this section.
 =====Displacement===== =====Displacement=====
-Displacement gives the offset for memory operands. Depending on the addressing mode, it can be the direct memory address or an additional offset added to the contents of the base, index register or both. Displacement can be 1, 2, or 4 bytes long. Some instructions allow using an 8-byte displacement. In these instructions, there is no immediate field.+Displacement gives the offset for memory operands. Depending on the addressing mode, it can be a direct memory address or an additional offset added to the contents of the base register, index register, or both. Displacement can be 1, 2, or 4 bytes long. Some instructions allow the use of an 8-byte displacement. In these instructions, there is no immediate field.
  
 =====Immediate===== =====Immediate=====
 Some instructions require an immediate value. The instruction determines the length of the immediate value. The immediate can be 1, 2, 4 or 8 bytes long. When an 8-byte immediate value is encoded, no displacement can be encoded. Some instructions require an immediate value. The instruction determines the length of the immediate value. The immediate can be 1, 2, 4 or 8 bytes long. When an 8-byte immediate value is encoded, no displacement can be encoded.
  
-<note>For detailed information on instructions encoding, please refer to the documentation provided by Intel and AMD. You can also find interesting information on websites: X86 Opcode and Instruction Reference ((http://ref.x86asm.net/index.html)) by +<note>For detailed information on instruction encoding, please refer to the documentation provided by Intel and AMD. You can also find interesting information on websites: X86 Opcode and Instruction Reference ((http://ref.x86asm.net/index.html)) by 
 MazeGen, x86 and amd64 instruction reference ((https://www.felixcloutier.com/x86/)) by Félix Cloutier.</note> MazeGen, x86 and amd64 instruction reference ((https://www.felixcloutier.com/x86/)) by Félix Cloutier.</note>
  
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