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--- en:multiasm:papc:chapter_6_5 [2026/01/15 14:34] – ktokarz
+++ en:multiasm:papc:chapter_6_5 [2026/02/27 01:43] (current) – [Base addressing] jtokarz
@@ Line 74: / Line 74: @@
 The code shows other examples of base addressing.
 <code asm>
-; copy one byte from the data segment in memory at the address from the BX register to AL
+; copy one byte from the data segment in memory at the address from
+; the BX register to AL
 mov al, [bx]
-; copy two bytes from the data segment in memory at the address from the EBX register to AX
+; copy two bytes from the data segment in memory at the address from
+; the EBX register to AX
 mov ax, [ebx]
@@ Line 179: / Line 181: @@
 <code asm>
 ; copy one byte from the data segment in the memory at the address calculated
-; as the sum of the base (BX) register, the index (SI) register and a displacement to AL
+; as the sum of the base (BX) register,
+; the index (SI) register and a displacement to AL
 mov al, [bx] + [si] + table
 mov al, [bx + si] + table
@@ Line 273: / Line 276: @@
 </figure>
-The 32-bit architecture makes the choice of registers much more flexible, and any of the eight registers (including the stack pointer) can be used as the base register. Here, the stack segment is chosen if the base register is EBP or ESP. Index register can be any of the general-purpose registers except of stack pointer. The index register can be scaled by a factor of 1, 2, 4 or 8. Additional displacement can be unused or can be encoded as an 8, 16 or 32-bit signed value.
+The 32-bit architecture makes the choice of registers much more flexible, and any of the eight registers (including the stack pointer) can be used as the base register. Here, the stack segment is chosen if the base register is EBP or ESP. The index register can be any of the general-purpose registers except the stack pointer. The index register can be scaled by a factor of 1, 2, 4 or 8. Additional displacement can be unused or can be encoded as an 8, 16 or 32-bit signed value.
 In the 64-bit architecture, any of the sixteen general-purpose registers can be the base register. As in 32-bit processors index register can not be the stack pointer and can be scaled by 1, 2, 4 or 8. Additional displacement can be unused or encoded as an 8, 16 or 32-bit signed number.
@@ Line 280: / Line 283: @@
 <figure effectiveIA32>
-{{ :en:multiasm:cs:effective_IA32.png?600 |Illustration of possible combination of base and index registers in indirect addressing mode in IA32 processor}}
+{{ :en:multiasm:cs:effective_IA32.png?600 |Illustration of a possible combination of base and index registers in indirect addressing mode in the IA32 processor}}
 <caption>Possible combination of registers in indirect addressing mode in IA32 architecture</caption>
+</figure>
+In x64, new R8 - R16 registers can also be used for address calculation, so the schematic of the effective address calculation looks like in the figure {{ref>effectivex64}}.
+<figure effectivex64>
+{{ :en:multiasm:cs:effective_x64.png?600 |Illustration of a possible combination of base and index registers in indirect addressing mode in the x64 processor}}
+<caption>Possible combination of registers in indirect addressing mode in x64 architecture</caption>
 </figure>

en/multiasm/papc/chapter_6_5.1768480464.txt.gz · Last modified: 2026/01/15 14:34 by ktokarz