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--- en:multiasm:papc:chapter_6_5 [2025/08/20 12:55] – [Addressing Modes in Instructions] ktokarz
+++ en:multiasm:papc:chapter_6_5 [2026/02/27 01:43] (current) – [Base addressing] jtokarz
@@ Line 1: / Line 1: @@
 ====== Addressing Modes in Instructions ======
-Addressing mode specifies how the processor reaches the data in the memory. The x86 architecture implements immediate, direct and indirect memory addressing. Indirect addressing can use a single or two registers and a constant to calculate the final address. The addressing mode takes the names of the registers used. The 32-bit mode makes the choice of the register for addressing more flexible and enhances addressing with the possibility of scaling: multiplying one register by a small constant. In 64-bit mode, addressing relative to the instruction pointer was added for easy relocation of programs in memory. In this chapter, we will focus on the details of all addressing modes in 16, 32 and 64-bit processors.
+Addressing mode specifies how the processor reaches the data in the memory. The x86 architecture implements immediate, direct and indirect memory addressing. Indirect addressing can use a single or two registers and a constant to calculate the final address.
-In each addressing mode, we are using the simple examples with the mov instruction. The move instruction copies data from the source operand to the destination operand. The order of the operands in instructions is similar to that of high-level languages. The left operand is the destination, the right operand is the source, as in the following example:
+In 16-bit mode, only four registers can be used for indirect addressing: BX, BP, SI and DI.
+In 32-bit mode, the choice of the register for addressing is much more flexible and addressing is enhanced with the possibility of scaling: multiplying one register by a small constant. In 64-bit mode, addressing relative to the instruction pointer was added for easy relocation of programs in memory. In this chapter, we will focus on the details of all addressing modes in 16, 32 and 64-bit processors.
+In each addressing mode, we are using simple examples with the mov instruction. The move instruction copies data from the source operand to the destination operand. The order of the operands in instructions is similar to that of high-level languages. The left operand is the destination, the right operand is the source, as in the following example:
 <code asm>
 mov destination, source
@@ Line 53: / Line 55: @@
 ===== Indirect addressing =====
-In the x86 architecture, there is a possibility to use one or two registers in one instruction to calculate the effective address, which is the final offset within the current segment (or section). In case of the use of two registers, one of them is called the base register, the second one is called the index register.
+In the x86 architecture, there is a possibility to use one or two registers in one instruction to calculate the effective address, which is the final offset within the current segment (or section). In the case of the use of two registers, one of them is called the base register, the second one is called the index register.
 In 16-bit processors, the base registers can be BX and BP only, while the index registers can be SI or DI. If BP is used, the processor automatically chooses the stack segment by default. For BX used as the base register, or for instructions with an index register only, the processor accesses the data segment by default.
 The 32-bit architecture makes the choice of registers much more flexible, and any of the eight registers (including the stack pointer) can be used as the base register. Here, the stack segment is chosen if the base register is EBP or ESP. The index register can be any of the general-purpose registers, excluding the stack pointer. Additionally, the index register can be scaled by a factor of 1, 2, 4 or 8.
@@ Line 72: / Line 74: @@
 The code shows other examples of base addressing.
 <code asm>
-; copy one byte from the data segment in memory at the address from the BX register to AL
+; copy one byte from the data segment in memory at the address from
+; the BX register to AL
 mov al, [bx]
-; copy two bytes from the data segment in memory at the address from the EBX register to AX
+; copy two bytes from the data segment in memory at the address from
+; the EBX register to AX
 mov ax, [ebx]
@@ Line 177: / Line 181: @@
 <code asm>
 ; copy one byte from the data segment in the memory at the address calculated
-; as the sum of the base (BX) register, the index (SI) register and a displacement to AL
+; as the sum of the base (BX) register,
+; the index (SI) register and a displacement to AL
 mov al, [bx] + [si] + table
 mov al, [bx + si] + table
@@ Line 271: / Line 276: @@
 </figure>
-The 32-bit architecture makes the choice of registers much more flexible, and any of the eight registers (including the stack pointer) can be used as the base register. Here, the stack segment is chosen if the base register is EBP or ESP. Index register can be any of the general-purpose registers except of stack pointer. The index register can be scaled by a factor of 1, 2, 4 or 8. Additional displacement can be unused or can be encoded as an 8, 16 or 32-bit signed value.
+The 32-bit architecture makes the choice of registers much more flexible, and any of the eight registers (including the stack pointer) can be used as the base register. Here, the stack segment is chosen if the base register is EBP or ESP. The index register can be any of the general-purpose registers except the stack pointer. The index register can be scaled by a factor of 1, 2, 4 or 8. Additional displacement can be unused or can be encoded as an 8, 16 or 32-bit signed value.
 In the 64-bit architecture, any of the sixteen general-purpose registers can be the base register. As in 32-bit processors index register can not be the stack pointer and can be scaled by 1, 2, 4 or 8. Additional displacement can be unused or encoded as an 8, 16 or 32-bit signed number.
@@ Line 278: / Line 283: @@
 <figure effectiveIA32>
-{{ :en:multiasm:cs:effective_IA32.png?600 |Illustration of possible combination of base and index registers in indirect addressing mode in IA32 processor}}
+{{ :en:multiasm:cs:effective_IA32.png?600 |Illustration of a possible combination of base and index registers in indirect addressing mode in the IA32 processor}}
 <caption>Possible combination of registers in indirect addressing mode in IA32 architecture</caption>
+</figure>
+In x64, new R8 - R16 registers can also be used for address calculation, so the schematic of the effective address calculation looks like in the figure {{ref>effectivex64}}.
+<figure effectivex64>
+{{ :en:multiasm:cs:effective_x64.png?600 |Illustration of a possible combination of base and index registers in indirect addressing mode in the x64 processor}}
+<caption>Possible combination of registers in indirect addressing mode in x64 architecture</caption>
 </figure>

en/multiasm/papc/chapter_6_5.1755683739.txt.gz · Last modified: 2025/08/20 12:55 by ktokarz