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en:multiasm:papc:chapter_6_5 [2026/02/27 01:43] – [Base addressing] jtokarzen:multiasm:papc:chapter_6_5 [2026/06/22 12:14] (current) – pczekalski
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 ====== Addressing Modes in Instructions ====== ====== Addressing Modes in Instructions ======
-Addressing mode specifies how the processor reaches the data in the memory. The x86 architecture implements immediate, direct and indirect memory addressing. Indirect addressing can use a single or two registers and a constant to calculate the final address. +Addressing mode specifies how the processor accesses data in memory. The x86 architecture implements immediate, direct and indirect memory addressing. Indirect addressing can use one or two registers and a constant to compute the final address. 
 In 16-bit mode, only four registers can be used for indirect addressing: BX, BP, SI and DI. In 16-bit mode, only four registers can be used for indirect addressing: BX, BP, SI and DI.
-In 32-bit mode, the choice of the register for addressing is much more flexible and addressing is enhanced with the possibility of scaling: multiplying one register by a small constant. In 64-bit mode, addressing relative to the instruction pointer was added for easy relocation of programs in memory. In this chapter, we will focus on the details of all addressing modes in 16, 32 and 64-bit processors.+In 32-bit mode, the choice of the register for addressing is much more flexible and addressing is enhanced with the possibility of scaling: multiplying one register by a small constant. In 64-bit mode, addressing relative to the instruction pointer was added to facilitate the relocation of programs in memory. In this chapter, we will focus on the details of all addressing modes in 16, 32 and 64-bit processors.
 In each addressing mode, we are using simple examples with the mov instruction. The move instruction copies data from the source operand to the destination operand. The order of the operands in instructions is similar to that of high-level languages. The left operand is the destination, the right operand is the source, as in the following example: In each addressing mode, we are using simple examples with the mov instruction. The move instruction copies data from the source operand to the destination operand. The order of the operands in instructions is similar to that of high-level languages. The left operand is the destination, the right operand is the source, as in the following example:
 <code asm> <code asm>
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 </code> </code>
 <note> <note>
-Calculating the addresses for control transfer instructions, including jumps and procedure calls, will be described in the section about these instructions.+The calculation of addresses for control-transfer instructions, including jumps and procedure calls, will be described in the section on these instructions.
 </note> </note>
 ===== Immediate addressing ===== ===== Immediate addressing =====
-The immediate argument is a constant encoded as part of the instruction. This means that this value is encoded in a code section of the program and can't be modified during program execution. +The immediate argument is a constant encoded in the instruction. This means that this value is encoded in a code section of the program and can't be modified during program execution. 
-In 16-bit mode, the size of the constant can be 8 or 16 bits, and in 32- and 64-bit mode, it can be up to 32 bits. The use of the immediate operand depends on the instruction. It can be, for example, a numerical constant, an offset of the address or additional displacement used for efficient address calculation, a value which specifies the number of iterations in shift instructions, a mask for choosing the elements of the vector to operate with or a modifier which influences the instruction behaviour. Please refer to the specific instruction documentation for the detailed description.+In 16-bit mode, the size of the constant can be 8 or 16 bits, and in 32- and 64-bit mode, it can be up to 32 bits. The use of the immediate operand depends on the instruction. It can be, for example, a numerical constant, an address offset or additional displacement used for efficient address calculation, a value that specifies the number of iterations in shift instructions, a mask for selecting the elements of the vector to operate on, or a modifier that influences the instruction behaviour. Please refer to the specific instruction documentation for the detailed description.
 The examples of instructions using immediate addressing The examples of instructions using immediate addressing
 <code asm> <code asm>
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 </code> </code>
 ===== Direct addressing ===== ===== Direct addressing =====
-In direct addressing mode, the data is reached by specifying the target offset (displacement) as a constant. The processor uses this offset together with the appropriate segment register to access the byte in memory. The displacement can be specified in the instruction as a number, a previously defined constant or a constant expression. With segmentation enabled, it is possible to use the segment prefix to select the segment register we want to use. The example instructions which use numbers or a variable name as the displacement are shown in the following code and presented in figure {{ref>directx86}}.+In direct addressing mode, the data is reached by specifying the target offset (displacement) as a constant. The processor uses this offset together with the appropriate segment register to access the byte in memory. The displacement can be specified in the instruction as a number, a previously defined constant or a constant expression. With segmentation enabled, it is possible to use the segment prefix can be used to select the segment register we want to use. The example instructions which use numbers or a variable name as the displacement are shown in the following code and presented in figure {{ref>directx86}}.
 <code asm> <code asm>
 ; copy one byte from the BL register to memory address 0800h in the data segment ; copy one byte from the BL register to memory address 0800h in the data segment
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 ===== x64 RIP-relative direct addressing ===== ===== x64 RIP-relative direct addressing =====
-64-bit processors have some specific addressing modes. The default mode for direct addressing mode in the x64 architecture is addressing relative to the RIP register. If there is no base or index register in the instruction, the address is encoded as a 32-bit signed value. This value represents the distance between the data byte in memory and the address of the next instruction (current value of RIP).+64-bit processors have some specific addressing modes. The default direct addressing mode in the x64 architecture is relative to the RIP register. If there is no base or index register in the instruction, the address is encoded as a 32-bit signed value. This value represents the distance between the data byte in memory and the address of the next instruction (current value of RIP).
 In figure {{ref>directRIPrelativex64}}, the RIP relative addressing where the variable is moved to AL is shown. In figure {{ref>directRIPrelativex64}}, the RIP relative addressing where the variable is moved to AL is shown.
  
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 ===== x64 32-bit direct addressing mode ===== ===== x64 32-bit direct addressing mode =====
-In this mode, the instruction holds the 32-bit signed value, which is sign-extended to 64 bits by the processor. This limits the addressing space to two areas. The first region starts from the address 0 and can reach 2GB of memory. The second is 2GB at the very end of the entire address space. As a 2GB memory size is insufficient for modern operating systems, this addressing mode is not supported by Windows compilers. MASM can use this mode in conjunction with a base or index register.+In this mode, the instruction holds the 32-bit signed value, which is sign-extended to 64 bits by the processor. This limits the addressing space to two areas. The first region starts at address 0 and can address up to 2GB of memory. The second is 2GB at the very end of the entire address space. Because 2GB of memory is insufficient for modern operating systems, this addressing mode is not supported by Windows compilers. MASM can use this mode in conjunction with a base or index register.
  
 ===== x64 64-bit direct addressing ===== ===== x64 64-bit direct addressing =====
-In this mode, the address is a 64-bit unsigned value. As in general, the arguments of the instruction are 32-bit in length, this addressing mode can be used only with a specific version of the MOV instruction and only with the accumulator (AL, AX, EAX, RAX).+In this mode, the address is a 64-bit unsigned value. As the arguments of the instruction are generally 32-bit, this addressing mode can be used only with a specific version of the MOV instruction and only with the accumulator (AL, AX, EAX, RAX).
 MASM assembler does not use this mode. MASM assembler does not use this mode.
  
  
 ===== Indirect addressing ===== ===== Indirect addressing =====
-In the x86 architecture, there is a possibility to use one or two registers in one instruction to calculate the effective address, which is the final offset within the current segment (or section). In the case of the use of two registers, one of them is called the base register, the second one is called the index register.  +In the x86 architecture, it is possible to use one or two registers in a single instruction to compute the effective address, which is the final offset within the current segment (or section). In the case of the use of two registers, one of them is called the base register, and the second one is called the index register.  
-In 16-bit processors, the base registers can be BX and BP only, while the index registers can be SI or DI. If BP is used, the processor automatically chooses the stack segment by default. For BX used as the base register, or for instructions with an index register only, the processor accesses the data segment by default. +In 16-bit processors, the base registers are BX and BP only, while the index registers are SI and DI. If BP is used, the processor automatically selects the stack segment. For BX used as the base register, or for instructions that use only an index register, the processor accesses the data segment by default. \\
 The 32-bit architecture makes the choice of registers much more flexible, and any of the eight registers (including the stack pointer) can be used as the base register. Here, the stack segment is chosen if the base register is EBP or ESP. The index register can be any of the general-purpose registers, excluding the stack pointer. Additionally, the index register can be scaled by a factor of 1, 2, 4 or 8. The 32-bit architecture makes the choice of registers much more flexible, and any of the eight registers (including the stack pointer) can be used as the base register. Here, the stack segment is chosen if the base register is EBP or ESP. The index register can be any of the general-purpose registers, excluding the stack pointer. Additionally, the index register can be scaled by a factor of 1, 2, 4 or 8.
-In the 64-bit architecture, which introduces eight additional registers, any of the sixteen general-purpose registers can be the base register or index register (excluding the stack pointer, which can be base only). In the following sections, we will show examples of all possible addressing modes.+In the 64-bit architecture, which introduces eight additional registers, any of the sixteen general-purpose registers can serve as the base or index register (excluding the stack pointer, which can be used as a base only). In the following sections, we will show examples of all possible addressing modes.
  
  
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 ===== Base addressing with displacement ===== ===== Base addressing with displacement =====
-Base addressing mode with displacement uses the base register with an additional constant added. So the final effective address is a sum of the content of the base register and the constant. It can be interpreted as the base register holds the address of the data table, and the constant is an offset of the byte in the table.+Base addressing mode with displacement uses the base register and adds an additional constant. So the final effective address is the sum of the base register's contents and the constant. It can be interpreted as the base register holding the address of the data table, and the constant is an offset into the table.
 In figure {{ref>basedispx86}}, the use of BX as the base register with additional displacement is shown to transfer data from memory to AL. In figure {{ref>basedispx86}}, the use of BX as the base register with additional displacement is shown to transfer data from memory to AL.
  
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 </code> </code>
 ===== Index addressing with displacement ===== ===== Index addressing with displacement =====
-Index addressing mode with displacement uses the index register with an additional constant added. So the final effective address is a sum of the content of the index register and the constant. It can be interpreted as the address of the data table is a constant, and the index register is an offset of the byte in a table.+Index addressing mode with displacement uses the index register with an additional constant added. So the final effective address is the sum of the index register's contents and the constant. It can be interpreted as the address of the data table is a constant, and the index register is an offset of the byte in a table.
 In figure {{ref>indexdispx86}}, the use of DI as the index register with additional displacement is shown to transfer data from memory to AL. In figure {{ref>indexdispx86}}, the use of DI as the index register with additional displacement is shown to transfer data from memory to AL.
  
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 </figure> </figure>
  
-MASM assembler accepts different notations of the base + index registers combination, as shown in the code. In the x86, the order of registers written in the instruction is irrelevant.+The MASM assembler accepts different notations for the base + index register combination, as shown in the code. On x86, the order of registers in the instruction is irrelevant.
 <code asm> <code asm>
 ; copy one byte from the data segment in the memory at the address calculated  ; copy one byte from the data segment in the memory at the address calculated 
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 In 32- or 64-bit processors, the first register used in the instruction is the base register, and the second is the index register. In 32- or 64-bit processors, the first register used in the instruction is the base register, and the second is the index register.
-While segmentation is enabled use of EBP or ESP as a base register determines the segment register choice. Notice that it is possible to use the same register as base and index in one instruction.+While segmentation is enabled, the use of EBP or ESP as the base register determines the choice of segment register. Notice that it is possible to use the same register as base and index in one instruction.
 <code asm> <code asm>
 ; copy one byte from the data or stack segment in memory at the address calculated  ; copy one byte from the data or stack segment in memory at the address calculated 
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 </code> </code>
 ===== Base Indexed addressing with displacement ===== ===== Base Indexed addressing with displacement =====
-In this addressing mode, the combination of two registers with an additional constant is used. In a 16-bit processor, the base register BX or BP, and the index register SI or DI. The constant can be encoded as an 8- or 16-bit value. In such a processor, this is the most complex mode available. In a 32- or 64-bit processor, any register can be the base, and all except the stack pointer can be the index. The constant is up to a 32-bit signed value. The final effective address is the sum of the contents of two registers and the displacement. +In this addressing mode, the combination of two registers with an additional constant is used. In a 16-bit processor, the base register is BX or BP, and the index register is SI or DI. The constant can be encoded as an 8- or 16-bit value. In such a processor, this is the most complex mode available. In a 32- or 64-bit processor, any register can be the base, and all except the stack pointer can be the index. The constant is up to a 32-bit signed value. The final effective address is the sum of the contents of two registers and the displacement. 
-In figure {{ref>baseindexdispx86}}, the use of BX as the base and SI as the index register with displacement to transfer data from memory to AL is shown. It can be interpreted as the constant is the address of the table of structures, the base register holds the offset of the structure in a table, and the index register keeps the offset of an element within the structure.+In figure {{ref>baseindexdispx86}}, the use of BX as the base and SI as the index register with displacement to transfer data from memory to AL is shown. It can be interpreted as follows: the constant is the address of the table of structures, the base register holds the offset of the structure in the table, and the index register holds the offset of an element within the structure.
  
 <figure baseindexdispx86> <figure baseindexdispx86>
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 </figure> </figure>
  
-MASM assembler accepts different notations of the base + index + displacement, as shown in the code. In the x86, the order of registers written in the instruction is irrelevant.+MASM assembler accepts different notations of the base + index + displacement, as shown in the code. On x86, the order of registers in the instruction is irrelevant.
 <code asm> <code asm>
 ; copy one byte from the data segment in the memory at the address calculated  ; copy one byte from the data segment in the memory at the address calculated 
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 </code> </code>
  
-In 32- or 64-bit processors, the first register used in the instruction is the base register, and the second is the index register. While segmentation is enabled, the use of EBP or ESP as a base register determines the segment register choice. The displacement can be placed at any position in the address argument expression. Some examples are shown below.+In 32- or 64-bit processors, the first register used in the instruction is the base register, and the second is the index register. When segmentation is enabled, the use of EBP or ESP as the base register determines the choice of segment register. The displacement can be placed at any position in the address argument expression. Some examples are shown below.
 <code asm> <code asm>
 ; copy one byte from the data or stack segment in memory at the address calculated  ; copy one byte from the data or stack segment in memory at the address calculated 
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 ===== Index addressing with scaling ===== ===== Index addressing with scaling =====
-Index addressing mode with scaling uses the index register multiplied by a simple constant of 1, 2, 4 or 8. This addressing mode is available for 32- or 64-bit processors and can use any general-purpose register except of stack pointer.+Index addressing mode with scaling uses the index register multiplied by a simple constant of 1, 2, 4 or 8. This addressing mode is available for 32- or 64-bit processors and can use any general-purpose register except the stack pointer.
 In figure {{ref>indexscaleIA32}}, the use of EBX as the index register with a scaling factor of 2 is shown to transfer data from memory to AL. In figure {{ref>indexscaleIA32}}, the use of EBX as the index register with a scaling factor of 2 is shown to transfer data from memory to AL.
  
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 </figure> </figure>
  
-Because in these instructions, there is no base register used, if there is segmentation enabled, the data segment is always chosen.+Because these instructions lack a base register, when segmentation is enabled, the data segment is always selected.
 <code asm> <code asm>
 ; copy one byte from the data or stack segment in memory at the address calculated  ; copy one byte from the data or stack segment in memory at the address calculated 
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 </code> </code>
 ===== Base Indexed addressing with scaling ===== ===== Base Indexed addressing with scaling =====
-Base indexed addressing mode with scaling uses the sum of the base register with the content of the index register multiplied by a simple constant of 1, 2, 4 or 8. This addressing mode is available for 32- or 64-bit processors and can use any general-purpose register as base and almost any general-purpose register as index, except of stack pointer. +Base-indexed addressing mode with scaling uses the sum of the base register and the content of the index register, multiplied by a simple constant of 1, 2, 4, or 8. This addressing mode is available for 32- or 64-bit processors and can use any general-purpose register as the base and almost any general-purpose register as the index, except for the stack pointer. 
-The figure {{ref>baseindexscaleIA32}} presents the use of EDI register as base, EAX as the index register with a scaling factor of 4 to transfer data from memory to AL.+The figure {{ref>baseindexscaleIA32}} shows the use of the EDI register as the base, EAX as the index register, and a scaling factor of 4 to transfer data from memory to AL.
  
 <figure baseindexscaleIA32> <figure baseindexscaleIA32>
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 </figure> </figure>
  
-The scaled register is assumed as the index, the other one is the base (even if it is not used first in the instruction). While segmentation is enabled, the use of EBP or ESP as a base register determines the segment register choice.+The scaled register is assumed to be the index; the other one is the base (even if it is not used first in the instruction). When segmentation is enabled, the use of EBP or ESP as the base register determines the choice of segment register.
 <code asm> <code asm>
 ; copy one byte from the data or stack segment in memory at the address calculated  ; copy one byte from the data or stack segment in memory at the address calculated 
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 </code> </code>
 ===== Base Indexed addressing with displacement and scaling ===== ===== Base Indexed addressing with displacement and scaling =====
-Base indexed addressing mode with displacement and scaling uses the sum of the base register, the content of the index register multiplied by a simple constant of 1, 2, 4 or 8, and an additional constant. This addressing mode is available for 32- or 64-bit processors and can use any general-purpose register as base and almost any general-purpose register as index, except of stack pointer. The displacement can be up to a 32-bit signed value, even in a 64-bit processor. +Base indexed addressing mode with displacement and scaling uses the sum of the base register, the content of the index register multiplied by a simple constant of 1, 2, 4 or 8, and an additional constant. This addressing mode is available for 32- or 64-bit processors and can use any general-purpose register as the base and almost any general-purpose register as the index, except for the stack pointer. The displacement can be up to a 32-bit signed value, even in a 64-bit processor. 
-The figure {{ref>baseindexdispscaleIA32}} presents the use of EDI register as base, EAX as the index register with a scaling factor of 4 to transfer data from memory to AL. The interpretation is similar to the base-indexed addressing mode with displacement for the x86 16-bit machine. The constant is the address of the beginning of the table of structures, the base register contains the offset of the structure, index register holds the scaled number of the element in a structure pointing to the chosen byte.+The figure {{ref>baseindexdispscaleIA32}} shows the use of the EDI register as the base, EAX as the index register, and a scaling factor of 4 to transfer data from memory to AL. The interpretation is similar to the base-indexed addressing mode with displacement for the x86 16-bit machine. The constant is the address of the beginning of the table of structures; the base register contains the offset of the structure; the index register holds the scaled index of the element in the structure, pointing to the chosen byte.
  
 <figure baseindexdispscaleIA32> <figure baseindexdispscaleIA32>
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 </figure> </figure>
  
-As in the base indexed mode with scaling without displacement, the scaled register is assumed as the index, and the other one is the base (even if it is not used first in the instruction). While segmentation is enabled, the use of EBP or ESP as a base register determines the segment register choice. The displacement can be placed at any position in the instruction.+As in the base indexed mode with scaling without displacement, the scaled register is assumed as the index, and the other one is the base (even if it is not used first in the instruction). When segmentation is enabled, the use of EBP or ESP as the base register determines the choice of segment register. The displacement can be placed at any position in the instruction.
 <code asm> <code asm>
 ; copy one byte from the data or stack segment in memory at the address calculated  ; copy one byte from the data or stack segment in memory at the address calculated 
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 ===== Summary for indirect addressing ===== ===== Summary for indirect addressing =====
-In 16-bit processors, the base registers can be BX and BP only. The first one is used to access the data segment, the second one automatically chooses the stack segment by default. The additional offset can be unused or can be encoded as an 8 or 16-bit signed value. The schematic of the x86 effective address calculation for indirect address generation is shown in figure {{ref>effectivex86}}+In 16-bit processors, the base registers can be BX and BP only. The first one is used to access the data segment, and the second one automatically chooses the stack segment by default. The additional offset can be left unused or encoded as an 8- or 16-bit signed value. The schematic of the x86 effective address calculation for indirect address generation is shown in figure {{ref>effectivex86}}
  
 <figure effectivex86> <figure effectivex86>
-{{ :en:multiasm:cs:effective_x86.png?600 |Illustration of possible combination of base and index registers in effective address calculation for indirect addressing mode in x86 processor}}+{{ :en:multiasm:cs:effective_x86.png?600 |Illustration of a possible combination of base and index registers in effective address calculation for indirect addressing mode in an x86 processor}}
 <caption>Possible combination of registers in effective address calculation for indirect addressing mode in x86 architecture</caption> <caption>Possible combination of registers in effective address calculation for indirect addressing mode in x86 architecture</caption>
 </figure> </figure>
  
-The 32-bit architecture makes the choice of registers much more flexible, and any of the eight registers (including the stack pointer) can be used as the base register. Here, the stack segment is chosen if the base register is EBP or ESP. The index register can be any of the general-purpose registers except the stack pointer. The index register can be scaled by a factor of 1, 2, 4 or 8. Additional displacement can be unused or can be encoded as an 8, 16 or 32-bit signed value.+The 32-bit architecture makes the choice of registers much more flexible, and any of the eight registers (including the stack pointer) can be used as the base register. Here, the stack segment is chosen if the base register is EBP or ESP. The index register can be any of the general-purpose registers except the stack pointer. The index register can be scaled by a factor of 1, 2, 4 or 8. Additional displacement can be unused or encoded as an 8-, 16-, or 32-bit signed value.
  
-In the 64-bit architecture, any of the sixteen general-purpose registers can be the base register. As in 32-bit processors index register can not be the stack pointer and can be scaled by 1, 2, 4 or 8. Additional displacement can be unused or encoded as an 8, 16 or 32-bit signed number.+In the 64-bit architecture, any of the sixteen general-purpose registers can be the base register. As in 32-bit processors, the index register cannot be the stack pointer and can be scaled by 1, 2, 4, or 8. Additional displacement can be left unused or encoded as an 8-, 16-, or 32-bit signed number.
  
 In figure {{ref>effectiveIA32}}, the schematic of the effective address calculation and use of registers for indirect addressing in the IA32 architecture is shown. In figure {{ref>effectiveIA32}}, the schematic of the effective address calculation and use of registers for indirect addressing in the IA32 architecture is shown.
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