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| en:multiasm:papc:chapter_6_2 [2025/04/29 18:38] – [Paging] ktokarz | en:multiasm:papc:chapter_6_2 [2026/05/27 09:58] (current) – [Segmented addressing in protected mode] ktokarz | ||
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| ===== Segmented addressing in real mode ===== | ===== Segmented addressing in real mode ===== | ||
| - | The 8086 can address the memory in so-called real mode only. In this mode, the address is calculated with two 16-bit elements: segment and offset. The 8086 implements four special registers to store the segment part of the address: CS, DS, ES, and SS. During program execution, all addresses are calculated relative to one of these registers. The program is divided into three segments containing the main elements. The code segment contains processor instructions and their immediate operands. The instructions | + | The 8086 can address the memory in so-called real mode only. In this mode, the address is calculated with two 16-bit elements: segment and offset. The 8086 implements four special registers to store the segment part of the address: CS, DS, ES, and SS. During program execution, all addresses are calculated relative to one of these registers. The program is divided into three segments containing the main elements. The code segment contains processor instructions and their immediate operands. The instructions' addresses |
| <figure realsegments> | <figure realsegments> | ||
| {{ : | {{ : | ||
| < | < | ||
| - | </ | + | </ |
| Although the 8086 processor has only four segment registers, there can be many segments defined in the program. The limitation is that the processor can access only four of them at the same time, as presented in Fig {{ref> | Although the 8086 processor has only four segment registers, there can be many segments defined in the program. The limitation is that the processor can access only four of them at the same time, as presented in Fig {{ref> | ||
| - | The address, which consists of two elements, the segment and the offset, is named a logical address. Both numbers which form a logical address are 16-bit numbers. So, how to calculate a 20-bit address with two 16-bit values? It is done in the following way. The segment part, taken always from the chosen segment register, is shifted four bit positions left. Four bits at the right side are filled with zeros, forming a 20-bit value. The offset value is added to the result of the shift. The result of the calculations is named the linear address. It is presented the Fig {{ref> | + | The address, which consists of two elements, the segment and the offset, is named a logical address. Both numbers which form a logical address are 16-bit numbers. So, how to calculate a 20-bit address with two 16-bit values? It is done in the following way. The segment part, taken always from the chosen segment register, is shifted four bit positions left. Four bits on the right side are filled with zeros, forming a 20-bit value. The offset value is added to the result of the shift. The result of the calculations is named the linear address. It is presented |
| <figure realcalc> | <figure realcalc> | ||
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| </ | </ | ||
| - | Although segmentation allows for advanced memory management and the implementation of memory protection, none of the popular operating systems, including Windows, Linux or MacOS, ever used it. In Windows, all segment registers, via descriptors, | + | Although segmentation allows for advanced memory management and the implementation of memory protection, none of the popular operating systems, including Windows, Linux-based, |
| <figure ia32flat> | <figure ia32flat> | ||
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| </ | </ | ||
| + | As currently built computers have significantly less physical memory than can be theoretically addressed with a 64-bit linear address, producers decided to limit the usable address space. That's why the 4-level paging mechanism recognises only 48 bits, leaving the upper bits unused. In 5-level paging, 57 bits are recognised. The most significant part of the address should have the value of the highest recognisable bit from the address. As the most significant bit of the number represents the sign, duplicating this bit is known as sign extension. | ||
| + | |||
| + | Sign-extended addresses having 48 or 57 recognised bits are known as canonical addresses, while others are non-canonical. It is presented in Fig {{ref> | ||
| + | |||
| + | <figure canonical> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| ===== Addressing in x64 processors ===== | ===== Addressing in x64 processors ===== | ||
| Because the segmentation wasn't used by operating systems software producers, AMD and Intel decided to abandon segmentation in 64-bit processors. For backwards compatibility, | Because the segmentation wasn't used by operating systems software producers, AMD and Intel decided to abandon segmentation in 64-bit processors. For backwards compatibility, | ||
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| In x64 bit mode, some instructions can use segment registers FS and GS as base registers. Operating systems' | In x64 bit mode, some instructions can use segment registers FS and GS as base registers. Operating systems' | ||
| </ | </ | ||
| - | The 64-bit mode theoretically allows the processor to address a vast memory of 16 exabytes in size. It is expected that such a big memory will not be installed in currently built computers, so the processors limit the available address space. | + | The 64-bit mode theoretically allows the processor to address a vast memory of 16 exabytes in size. It is expected that such a big memory will not be installed in currently built computers, so the processors limit the available address space, not only at the paging level but also physically, having a limited number of address bus lines. |
