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en:multiasm:papc:chapter_6_16 [2025/11/22 13:44] – [Cache temporal locality] ktokarzen:multiasm:papc:chapter_6_16 [Unknown date] (current) – external edit (Unknown date) 127.0.0.1
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-====== Optimisation (DRAFT) ======+====== Optimisation ======
 Optimisation strongly depends on the microarchitecture of the processor. Some optimisation recommendations change together with new versions of processors. Producers usually publish the most up-to-date recommendations. The last release of the Intel documentation is "Intel® 64 and IA-32 Architectures Optimization" ((https://www.intel.com/content/www/us/en/developer/articles/technical/intel64-and-ia32-architectures-optimization.html)). AMD published the document "Software Optimization Guide for the AMD Zen5 Microarchitecture" ((https://docs.amd.com/v/u/en-US/58455_1.00)). Optimisation strongly depends on the microarchitecture of the processor. Some optimisation recommendations change together with new versions of processors. Producers usually publish the most up-to-date recommendations. The last release of the Intel documentation is "Intel® 64 and IA-32 Architectures Optimization" ((https://www.intel.com/content/www/us/en/developer/articles/technical/intel64-and-ia32-architectures-optimization.html)). AMD published the document "Software Optimization Guide for the AMD Zen5 Microarchitecture" ((https://docs.amd.com/v/u/en-US/58455_1.00)).
 A selection of specific optimisation recommendations is described in this section. A selection of specific optimisation recommendations is described in this section.
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-===== Cache support instructions ===== +===== Cache utilisation ===== 
-In modern microarchitectures, the cache memory is essential for improving performance. In general, the processor handles cache memory in the most efficient way possible; however, it is easy to write a program that prevents the processor from utilising this mechanism effectively. The rules for helping processors to use cache to achieve the best performance are: +In modern microarchitectures, the cache memory is essential for improving performance. In general, the processor handles cache memory in the most efficient way possible; however, it is easy to write a program that prevents the processor from utilising this mechanism effectively.  
 +The cache works on two main principles:  
 +  * temporal locality 
 +  * spatial locality. 
 +The term temporal locality refers to the fact that if a program recently used a certain portion of data, it is likely to need it again soon. It means that if data is used, it remains in a cache for a certain amount of time until other data is loaded into the cache. It is efficient to keep data in a cache instead of reloading it.  
 +The term spatial locality refers to whether a program has recently accessed data at a particular address; likely, it will soon need data at the next address. The cache helps the program run faster by automatically prefetching data and code that will likely be used or executed soon.  
 +It is recommended to write the programs in any programming language, keeping these rules in mind. Some recommendations are listed below: 
 +  * The program should do as much work as possible on one small area of code and data; after doing the job, it can move to the next part. 
 +  * The program should avoid frequent jumping over distant regions of memory.  
 +  * While processing big multidimensional data arrays, keep in mind their placement in memory (row-wise or column-wise), which is specific to the programming language. 
 +  * Object-oriented programming helps to utilise cache because members of the class are grouped. 
 +===== Cache temporal locality ===== 
 + This feature helps improve performance in situations where the program uses the same variables repeatedly, e.g. in a loop. 
 +In a situation where the data processed exceeds half the size of a level 1 cache, it is recommended to use the non-temporal data move instructions **movntq** and **movntdq** to store data from registers to memory. These instructions are hints to the processor to omit the cache if possible. It doesn't mean that the data is immediately stored directly in memory. It can remain in the internal processor's buffers, and it is likely that the last version is not visible to other units of the computer. It is the programmer's responsibility to synchronise the data using the **sfence** (Store Fence) instruction.
  
 +===== Cache support instructions =====
 There are also instructions which allow the programmer to support the processor with cache utilisation. There are also instructions which allow the programmer to support the processor with cache utilisation.
   * **movntq** saving the contents of the MMX register, bypassing cache   * **movntq** saving the contents of the MMX register, bypassing cache
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   * **mfence** force the memory–cache synchronisation after load and store instructions   * **mfence** force the memory–cache synchronisation after load and store instructions
  
 +Some instructions are hints to the processor indicating that the programmer expects the data to be stored in cache rather than in memory, or they do not expect to use the data in cache anymore.
   * **prefetch** a hint to the processor, which indicates that the memory area should be considered higher in the hierarchy cache   * **prefetch** a hint to the processor, which indicates that the memory area should be considered higher in the hierarchy cache
   * **clflush** flushes a Cache Line from all levels of cache.   * **clflush** flushes a Cache Line from all levels of cache.
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-===== Cache temporal locality ===== +
-The term temporal locality refers to the fact that if data is used, it remains in a cache for a certain amount of time until other data is loaded into the cache. It is efficient to keep data in a cache instead of reloading it. This feature helps improve performance in situations where the program uses the same variables repeatedly, e.g. in a loop. +
-In a situation where the data processed exceeds half the size of a level 1 cache, it is recommended to use the non-temporal data move instructions **movntq** and **movntdq** to store data from registers to memory. These instructions are hints to the processor to omit the cache if possible. It doesn't mean that the data is immediately stored directly in memory. It can remain in the internal processor's buffers, and it is likely that the last version is not visible to other units of the computer. It is the programmer's responsibility to synchronise the data using the **sfence** (Store Fence) instruction.+
  
 ===== Further reading ===== ===== Further reading =====
en/multiasm/papc/chapter_6_16.1763811862.txt.gz · Last modified: by ktokarz
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