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Trace: • Components of Processor: Registers, ALU, Bus Control, Instruction Decoder • MASM Basics • Bluetooth BTBee • Specific Elements of the x86 and x64 Architectures

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en:multiasm:papc:chapter_6_15 [2026/02/20 11:36] – ktokarzen:multiasm:papc:chapter_6_15 [2026/02/20 11:49] (current) – [Cache temporal locality] ktokarz
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   * Object-oriented programming helps to utilise cache because members of the class are grouped.   * Object-oriented programming helps to utilise cache because members of the class are grouped.
 ===== Cache temporal locality ===== ===== Cache temporal locality =====
- This feature helps improve performance in situations where the program uses the same variables repeatedly, e.g. in a loop. +Cache temporal locality is the feature that helps improve performance in situations where the program uses the same variables repeatedly, e.g. in a loop. If the processed data exceeds half the size of a level 1 cache, it is recommended to use the non-temporal data move instructions **movntq** and **movntdq** to store data from registers to memory. These instructions are hints to the processor to omit the cache if possible. It doesn't mean that the data is immediately stored directly in memory. It can remain in the internal processor's buffers, and, likely, the last version is not visible to other units of the computer. It is the programmer's responsibility to synchronise the data using the **sfence** (Store Fence) instruction.
-In a situation where the data processed exceeds half the size of a level 1 cache, it is recommended to use the non-temporal data move instructions **movntq** and **movntdq** to store data from registers to memory. These instructions are hints to the processor to omit the cache if possible. It doesn't mean that the data is immediately stored directly in memory. It can remain in the internal processor's buffers, and it is likely that the last version is not visible to other units of the computer. It is the programmer's responsibility to synchronise the data using the **sfence** (Store Fence) instruction.+
  
 ===== Cache support instructions ===== ===== Cache support instructions =====
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 Fence instructions guarantee that the load and/or store instructions before the fence are completed before the corresponding instruction after the fence. Fence instructions guarantee that the load and/or store instructions before the fence are completed before the corresponding instruction after the fence.
-  * **spence** force the memory–cache synchronisation after store instructions+  * **sfence** force the memory–cache synchronisation after store instructions
   * **lfence** force the memory–cache synchronisation after load instructions   * **lfence** force the memory–cache synchronisation after load instructions
   * **mfence** force the memory–cache synchronisation after load and store instructions   * **mfence** force the memory–cache synchronisation after load and store instructions
en/multiasm/papc/chapter_6_15.1771580191.txt.gz · Last modified: by ktokarz
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