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--- en:multiasm:papc:chapter_6_10 [2026/02/18 11:29] – [Basic arithmetic instructions] ktokarz
+++ en:multiasm:papc:chapter_6_10 [2026/06/22 16:53] (current) – pczekalski
@@ Line 1: / Line 1: @@
 ====== FPU ======
-The Floating Point Unit is developed to speed up calculations on real numbers, encoded in a computer as floating-point numbers. At the beginning of the x86 processors' history, the FPU was a separate integrated circuit. Since the i486DX, it has been introduced as a standard element of each processor. The FPU operates on single, double or extended precision values, using its own set of registers and instructions. For details about FPU registers, please refer to the section "Register Set".
+The Floating Point Unit is designed to speed up calculations on real numbers, which are encoded in a computer as floating-point numbers. At the beginning of the history of x86 processors, the FPU was a separate integrated circuit. Since the i486DX, it has been a standard element of every processor. The FPU operates on single-, double-, or extended-precision values, using its own set of registers and instructions. For details on FPU registers, please refer to the "Register Set" section.
 <note>
-Although modern extensions for processors can currently perform calculations with real numbers faster with the use of vector instructions, they do not achieve the precision available with the extended precision encoding.
+Although modern extensions to processors can currently perform real-number calculations faster using vector instructions, they do not achieve the precision available with extended-precision encoding.
 </note>
-Registers in the FPU are organised as a stack with 8 levels of depth. Physical registers are named R0 - R8, while registers visible by the FPU take names ST(0) to ST(7). The ST(0), also referred to as ST, is always the top of the stack, while ST(7) is the bottom of the stack. The top of the stack is pointed to with three bits in the FPU status word register. Each time the data is loaded to the FPU, the stack top is decremented, and each time the data is popped off the stack, it is incremented. The initial state is as shown in figure {{ref>fpuinit}}.
+Registers in the FPU are organised as a stack with 8 levels of depth. Physical registers are named R0-R8, while registers visible to the FPU are named ST(0)-ST(7). The ST(0), also referred to as ST, is always the top of the stack, while ST(7) is the bottom of the stack. The top of the stack is pointed to with three bits in the FPU status word register. Each time data is loaded into the FPU, the stack top is decremented; each time data is popped from the stack, it is incremented. The initial state is as shown in figure {{ref>fpuinit}}.
 <figure fpuinit>
@@ Line 18: / Line 18: @@
 </figure>
-The stack organisation of registers makes it easier to implement math calculations according to the RPN (Reverse Polish Notation), also called postfix notation.
+The stack organisation of registers makes it easier to implement mathematical calculations using RPN (Reverse Polish Notation), also called postfix notation.
 Further in this section, we'll present the FPU coprocessor's instructions. They can be grouped as:
   * data transfer instructions,
@@ Line 29: / Line 29: @@
 ===== Data transfer instructions =====
-Data in the memory used by FPU can be stored as a single precision, double precision or double extended-precision floating point value or as an integer of the type word, double word, quadword, or 18-digit BCD number. The FPU always converts it into double-extended precision floating point while loading it into an internal register and converts the data to the required format while storing it back into memory.
+Data in the memory used by the FPU can be stored as a single-precision, double-precision, or double-extended-precision floating-point value, or as an integer of the type word, double word, quadword, or 18-digit BCD number. The FPU always converts it to double-extended-precision floating-point while loading it into an internal register, and converts the data to the required format while storing it back into memory.
-Loading instructions, always first decrement the stack top field in the status word register and next, load the value onto the new top of the register stack.
-The **fld** instruction loads a single precision, double precision or double extended-precision onto the FPU register stack. It can also copy data from other FPU register into ST. The **fild** instruction loads integer values of word, doubleword or quadword. The **fbld** instruction loads an 18-digit binary decimal encoded value.
+Loading instructions: always first decrement the stack top field in the status word register, then load the value onto the new top of the register stack.\\
-Store instructions take data off the FPU register stack and place it in the memory.
+The **fld** instruction loads a single precision, double precision or double extended-precision onto the FPU register stack. It can also copy data from other FPU registers into ST.\\
-The **fst** instruction stores a single precision or a double precision value to the memory. It can also copy a value to another FPU register. The **fstp** instruction also works with 80-bit double extended precision values and additionally pops data off the stack by incrementing the stack top field in the status word register. It can also copy a value to another FPU register, popping it off the FPU register stack.
+The **fild** instruction loads integer values of word, doubleword or quadword.\\
-The **fist** converts the value from the top of the FPU register stack into a word or doubleword integer and stores it in memory. The **fistp** also can store a 64-bit quadword integer and additionally pops the value from the stack top.
+The **fbld** instruction loads an 18-digit binary decimal encoded value.\\
-The **fbstp** pops value off the FPU register stack and writes it as an 80-bit BCD encoded integer in memory.
+Store instructions take data off the FPU register stack and place it in the memory.\\
+The **fst** instruction stores a single-precision or a double-precision value to the memory. It can also copy a value to another FPU register.\\
+The **fstp** instruction also works with 80-bit double extended precision values and additionally pops data off the stack by incrementing the stack top field in the status word register. It can also copy a value to another FPU register, popping it off the FPU register stack.\\
+The **fist** converts the value from the top of the FPU register stack into a word or doubleword integer and stores it in memory.\\
+The **fistp** can also store a 64-bit quadword integer and pop the value from the stack top.\\
+The **fbstp** pops a value from the FPU register stack and writes it as an 80-bit BCD-encoded integer to memory.
 <note>
-Please note that it is not possible to exchange values between the FPU stack and CPU registers directly. It is also not possible to load the constant encoded as an immediate value. You can do it with the use of temporal variables placed in memory.
+Please note that it is not possible to exchange values directly between the FPU stack and CPU registers. It is also not possible to load the constant encoded as an immediate value. You can do it using temporal variables stored in memory.
 </note>
-The **fxch** instruction exchanges values in two FPU registers, where one of them is the top of the stack. This instruction, used without any argument, exchanges ST and ST(1).
+The **fxch** instruction exchanges values in two FPU registers, where one of them is the top of the stack. This instruction, used without any argument, exchanges ST and ST(1).\\
-The **fcmov//cc//** instructions provide the conditional data transfer. They are introduced in the P6 processor to avoid conditional jumps. They test the condition based on flags in the EFLAGS register. The source operand can be any FPU register, while the destination is always ST(0). The **fcmov//cc//** instructions do not modify the stack top in the FPU.
+The **fcmov//cc//** instructions provide the conditional data transfer. They are introduced in the P6 processor to avoid conditional jumps. They test the condition based on flags in the EFLAGS register. The source operand can be any FPU register, while the destination is always ST(0).\\
+The **fcmov//cc//** instructions do not modify the stack top in the FPU.\\
 There are eight such instructions summarised in the table {{ref>fpufcmovcc}}
 <table fpufcmovcc>
@@ Line 57: / Line 64: @@
 </table>
 <note>
-Unordered means that at least one of the arguments of the comparison instruction does not represent a proper numerical value (is NaN).
+Unordered means that at least one of the arguments of the comparison instruction does not represent a proper numerical value (is ''NaN'').
 </note>
 ===== Load constants instructions =====
-Some constant values can be pushed onto the FPU register stack without the need to define them in memory. Such loading is faster than in instructions that access memory. They are summarised in the table {{ref>fload_constants}}.
+Some constant values can be pushed onto the FPU register stack without the need to define them in memory. Such loading is faster than loading from memory in instructions. They are summarised in the table {{ref>fload_constants}}.
 <table fload_constants>
 <caption>Load constants instructions</caption>
@@ Line 75: / Line 82: @@
 ===== Basic arithmetic instructions =====
-This group of instructions contains addition, subtraction, multiplication and division instructions in various versions. Arguments of these instructions determine their behaviour. Let's consider some examples.
+This group of instructions includes addition, subtraction, multiplication, and division in various forms. The arguments to these instructions determine their behaviour. Let's consider some examples.\\
-If the instruction has a single argument, it must be a memory argument, which specifies a single precision or a double precision floating point number. The result is always stored in ST(0). The version with two arguments works with registers only. The order of arguments determines the order of the calculation and result placement. For example, **fsub ST(0), ST(i)** subtracts ST(i) from ST(0) and stores the result in ST(0). The **fsub ST(i), ST(0)** subtracts ST(0) from ST(i) and stores the result in ST(i). The popped version with two arguments additionally pops the stack. For example, **fsubp ST(i), ST(0)** subtracts ST(0) from ST(i), stores the result in ST(i) and pops the stack. No argument version implies ST(1) as the destination and ST(0) as the source argument. For example, **fsubp** subtracts ST(0) from ST(1), stores the result in ST(1) and pops the stack. The result is then at the stack top. Basic arithmetic instructions are summarised in table {{ref>ffparithmetic}}, //float// represents the single precision argument in memory, //double// represents the double precision argument in memory. The ST(i) is the i-th FPU register.
+If the instruction has a single argument, it must be a memory argument that specifies a single- or double-precision floating-point number. The result is always stored in ST(0). The version with two arguments works only with registers. The order of arguments determines the order of the calculation and the placement of the result.
+For example, **fsub ST(0), ST(i)** subtracts ST(i) from ST(0) and stores the result in ST(0).\\
+The **fsub ST(i), ST(0)** subtracts ST(0) from ST(i) and stores the result in ST(i). The popped version with two arguments additionally pops the stack.\\
+For example, **fsubp ST(i), ST(0)** subtracts ST(0) from ST(i), stores the result in ST(i) and pops the stack. No argument version implies ST(1) as the destination and ST(0) as the source argument.\\
+For example, **fsubp** subtracts ST(0) from ST(1), stores the result in ST(1) and pops the stack. The result is then at the top of the stack. Basic arithmetic instructions are summarised in table {{ref>ffparithmetic}}, //float// represents the single precision argument in memory, //double// represents the double precision argument in memory. The ST(i) is the i-th FPU register.
 <table ffparithmetic>
 <caption>Basic floating point arithmetic instructions</caption>
@@ Line 154: / Line 166: @@
 </table>
-The basic arithmetic instructions also contain instructions for other calculations. The **fprem** and **fprem1** calculate the partial remainder obtained from dividing the value in the ST(0) register by the value in the ST(1) register. The **fabs** calculate the absolute value of ST(0). The **fchs** changes the sign of ST(0). The **frndint** rounds the ST(0) to an integer. The **fscale** scales ST(0) by a power of two taken from ST(1), while **fxtract** separates the value in ST(0) into the exponent placed in ST(0) and the significand, which is pushed onto the stack. As a result, the exponent is in ST(1) and the significand in ST(0). It is also possible to calculate the square root of ST(0) with the **sqrt** instruction.
+The basic arithmetic instructions also contain instructions for other calculations.\\
+The **fprem** and **fprem1** calculate the partial remainder obtained from dividing the value in the ST(0) register by the value in the ST(1) register.\\
+The **fabs** calculate the absolute value of ST(0).\\
+The **fchs** changes the sign of ST(0).\\
+The **frndint** rounds the ST(0) to an integer. \\
+The **fscale** scales ST(0) by a power of two taken from ST(1),\\
+while **fxtract** separates the value in ST(0) into the exponent placed in ST(0) and the significand, which is pushed onto the stack. As a result, the exponent is in ST(1) and the significand in ST(0).\\
+It is also possible to calculate the square root of ST(0) with the **sqrt** instruction.
 ===== Comparison instructions =====
-The comparison instructions compare two floating point values and set flags appropriate to the result. The operand of the **fcom** instruction can be a memory operand or another FPU register. It is always compared with the top of the stack. If no operand is specified, it compares ST(0) and ST(1). Popped version **fcomp** pops ST(0) off the stack. The instruction **fcompp** with double "P" at the end can't have any argument, compares ST(0) and ST(1) and pops both registers off the stack.
+The comparison instructions compare two floating-point values and set flags appropriate to the result.\\
-If one of the arguments is NaN, they generate the invalid arithmetic operand exception. To avoid unwanted exceptions, there are unordered versions of comparison instructions. These are **fucom**, **fucomp**, and **fucompp**. Unordered comparison instructions do not operate with memory arguments. Two instructions are implemented to compare integers. The **ficom** and **ficomp** have a single memory argument that can be a word or doubleword, which is compared with the top of the stack.
+The operand of the **fcom** instruction can be a memory operand or another FPU register. It is always compared with the top of the stack. If no operand is specified, it compares ST(0) and ST(1).\\
-Original instructions set flags C0, C2 and C3 in the FPU status word register. After implementing FPU as the integral unit of the processor, a new set of instructions appeared that set flags in the FLAGS register directly. There are **fcomi**, **fcomip**, **fucomi** and **fucomip**. Their first argument is always ST(0), the second is another FPU register.
+Popped version **fcomp** pops ST(0) off the stack. \\
-To the group of the comparison instructions also belong **fxam** and **ftst** instructions. The **fxam** instruction classifies the value of ST(0), while the **ftst** instruction compares ST(0) with the value of 0.0. They return the information in C0, C2 and C3 flags.
+The instruction **fcompp** with double "P" at the end can't have any argument, compares ST(0) and ST(1) and pops both registers off the stack.\\
+If one of the arguments is NaN, they generate the invalid arithmetic operand exception. To avoid unwanted exceptions, there are unordered versions of comparison instructions. These are **fucom**, **fucomp**, and **fucompp**. Unordered comparison instructions do not operate with memory arguments. Two instructions are implemented to compare integers.\\
+The **ficom** and **ficomp** have a single memory argument that can be a word or doubleword, which is compared with the top of the stack.\\
+The original instructions set flags C0, C2, and C3 in the FPU status word register. After implementing FPU as the integral unit of the processor, a new set of instructions appeared that directly set flags in the FLAGS register. There are **fcomi**, **fcomip**, **fucomi** and **fucomip**. Their first argument is always ST(0), the second is another FPU register.\\
+To the group of comparison instructions also belong **fxam** and **ftst** instructions. \\
+The **fxam** instruction classifies the value of ST(0), while the **ftst** instruction compares ST(0) with the value of 0.0. They return the information in C0, C2 and C3 flags.
 ===== Transcendental instructions =====
-The transcendental instructions perform calculations of advanced mathematical functions.
+The transcendental instructions perform calculations of advanced mathematical functions.\\
-The **fsin** instruction calculates the sine, while the **fcos** calculates the cosine of the argument stored in ST(0). The **fsincos** calculates both sine and cosine with the same instruction. The sine is returned in ST(1), the cosine in ST(0). The **fptan** instruction calculates the partial tangent and **fpatan** the partial arctangent. After calculating the tangent, the value of 1.0 is pushed onto the stack to make it easier to calculate cotangent afterwards by execution **fdivr** instruction. The partial means that this instruction handles only a limited range of input arguments.
+The **fsin** instruction calculates the sine, while the **fcos** calculates the cosine of the argument stored in ST(0).\\
+The **fsincos** calculates both sine and cosine with the same instruction. The sine is returned in ST(1), the cosine in ST(0).\\
+The **fptan** instruction calculates the partial tangent and **fpatan** the partial arctangent. After calculating the tangent, the value 1.0 is pushed onto the stack to make it easier to calculate the cotangent later by executing the **fdivr** instruction. The partial means that this instruction handles only a limited range of input arguments.\\
 The instructions for exponential and logarithmic functions are summarised in table {{ref>ftrans}}.
 <table ftrans>
@@ Line 175: / Line 202: @@
 ===== FPU control instructions =====
-The FPU control instructions help the programmer to save and restore the contents of chosen registers if there is a need to use them in an interrupt handler or inside a function. It is also possible to initialise the state of the FPU unit or clear errors.
+The FPU control instructions help the programmer to save and restore the contents of chosen registers if there is a need to use them in an interrupt handler or inside a function. It is also possible to initialise the FPU unit's state or clear errors.\\
-The **fincstp** increments and **fdecstp** decrements the FPU register stack pointer.
+The **fincstp** increments and **fdecstp** decrements the FPU register stack pointer.\\
-The following set of instructions can perform error checking while execution (instructions without "N") or perform the operation without checking for error conditions (instructions without "N").
+The following set of instructions can perform error checking while execution (instructions without "N") or perform the operation without checking for error conditions (instructions without "N").\\
-The **finit** and **fninit** initialise the FPU (after checking error conditions or without checking error conditions).
+The **finit** and **fninit** functions initialise the FPU (either after checking error conditions or without checking them).\\
-The **fclex** and **fnclex** clear floating-point exception flags.
+The **fclex** and **fnclex** clear floating-point exception flags.\\
-The **fstcw** and **fnstcw** store the FPU control word.
+The **fstcw** and **fnstcw** store the FPU control word.\\
-The **fldcw** loads the FPU control word.
+The **fldcw** loads the FPU control word.\\
-The **fstenv** and **fnstenr** store the FPU environment. The environment consists of the FPU control word, status
+The **fstenv** and **fnstenr** store the FPU environment. The environment consists of the FPU control word, status word, tag word, instruction pointer, data pointer, and last opcode register.\\
-word, tag word, instruction pointer, data pointer, and last opcode register.
+The **fldenv** loads the FPU environment.\\
-The **fldenv** loads the FPU environment.
+The **fsave** and **fnsave** save the FPU state. The state is the operating environment and full register stack.\\
-The **fsave** and **fnsave** save the FPU state. The state is the operating environment and full register stack.
+The **frstor** restores the FPU state.\\
-The **frstor** restores the FPU state.
+The **fstsw** and **fnstsw** store the FPU status word. There is no instruction for restoring the status word.\\
-The **fstsw** and **fnstsw** store the FPU status word. There is no instruction for restoring the status word.
+The **wait** or **fwait** waits for the FPU to finish the operation.\\
-The **wait** or **fwait** waits for the FPU to finish the operation.
+The **fnop** instruction is the no-operation instruction for the FPU.\\
-The **fnop** instruction is the no operation instruction for the FPU.

en/multiasm/papc/chapter_6_10.txt · Last modified: 2026/06/22 16:53 by pczekalski