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| en:multiasm:paarm:chapter_5_7 [2026/02/27 16:30] – [Interrupts] jtokarz | en:multiasm:paarm:chapter_5_7 [2026/05/27 09:36] (current) – [Interrupts] ktokarz |
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| * The rest of the IDs are for Shared Peripheral interrupts | * The rest of the IDs are for Shared Peripheral interrupts |
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| Practically, the Raspberry Pi 5 may have hundreds of interrupts from different sources in use, because the SoC chip BCM2712 have a lot of internal peripheral interrupts, the RP1 chip (the one that handles I/O lines and other peripherals on board) uses additional interrupts over PCIe bus. The Linux OS creates its own software interrupt, and finally, Linux combines them through the GIC. | Practically, the Raspberry Pi 5 may have hundreds of interrupts from different sources in use, because the SoC chip BCM2712 have a lot of internal peripheral interrupts, the RP1 chip (the one that handles I/O lines and other peripherals on board) uses additional interrupts over the PCIe bus. Linux creates its own software interrupt and finally, combines them through the GIC. |
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| The interrupts can be disabled and enabled. For example:\\ | The interrupts can be disabled and enabled. For example:\\ |
