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--- en:multiasm:paarm:chapter_5_6 [2025/12/03 23:26] – [Arithmetical instructions] eriks.klavins
+++ en:multiasm:paarm:chapter_5_6 [2026/02/27 16:23] (current) – jtokarz
@@ Line 55: / Line 55: @@
 <fc #800000>''ADD''</fc>   <fc #008000>''X3''</fc>, <fc #008000>''X4''</fc>, <fc #008000>''W5''</fc>, <fc #cd5c5c>''UXTW''</fc> <fc #6495ed>''@X3 = X4 + W5''</fc>
-{{:en:multiasm:paarm:addextended_1.jpg|}}
+{{ :en:multiasm:paarm:addextended_1.jpg?600 |The ADD instruction with extended registers}}
 <fc #800000>''ADDS''</fc>   <fc #008000>''X3''</fc>, <fc #008000>''X4''</fc>, <fc #008000>''W5''</fc>, <fc #cd5c5c>''UXTW''</fc> <fc #6495ed>''@X3 = X4 + W5 and update the status flags''</fc>
-{{:en:multiasm:paarm:addsextended_1.jpg|}}
+{{ :en:multiasm:paarm:addsextended_1.jpg?600 |The ADDS instruction with extended registers}}
 The machine code representation of the assembler instruction would be like:
@@ Line 100: / Line 100: @@
 In machine code, it is possible to determine the maximum value that can be added to a register. The ‘imm12’ bits limit the value to 0-4095. Besides that, the ‘sh’ bit allows to shift left (LSL) the immediate value by 12 bits.
-{{:en:multiasm:paarm:addimediate.jpg|}}
+{{ :en:multiasm:paarm:addimediate.jpg?600 |The ADDS (ADD) instructions with immediate value}}
 Examples with immediate the <fc #800000>''ADD''</fc> instruction
@@ Line 132: / Line 132: @@
 The final add instruction type adds two registers together, with one register shifted; the shift can be LSL (Logical Shift Left), LSR (Logical Shift Right), or ASR (Arithmetic Shift Right). The fourth shift option is not available. The number of bits in the ‘imm6’ field identifies the number of bits to be shifted for the ‘Rm’ register before it is added to the ‘Rn’ register.
-{{:en:multiasm:paarm:addshifted.jpg|}}
+{{ :en:multiasm:paarm:addshifted.jpg?600 |The ADDS (ADD) instruction with a shifted register}}
 Similar options are available for many other ARMv8 instructions. The instruction set documentation may provide the necessary information to determine the possibilities and restrictions on instruction usage. By examining the instruction's binary form, it is possible to identify its capabilities and limitations. Assembler code is converted to binary, and the final binary code for the instruction depends on the provided operands and, if available, options.
@@ Line 161: / Line 161: @@
 The register ''<fc #008000>X0</fc>'' holds a memory address. The data/value is loaded into the ''<fc #008000>W2</fc>'' register, and then the value is added to the ''<fc #008000>W1</fc>'' register value, after which the new value ''[<fc #008000>X0</fc>]+<fc #008000>W1</fc>'' is stored back into memory at the exact location pointed by ''[<fc #008000>X0</fc>]''. Basically, the ''<fc #008000>W2</fc>'' register now holds the ''[<fc #008000>X0</fc>]''- pointed data that was present before the ''<fc #008000>W1</fc>'' value was added. Similar instructions are available to perform atomic logic operations on the memory data.
-To copy content from one register to another, the ''<fc #800000>MOV</fc>'' instruction is used. The ''<fc #800000>FMOV</fc>'' instruction can also copy floating-point values. These instructions allow typecasting a floating-point value to an integer and vice versa.\\
+To copy content from one register to another, the ''<fc #800000>MOV</fc>'' instruction is used. The ''<fc #800000>FMOV</fc>'' instruction can also copy floating-point values. These instructions allow typecasting a floating-point value to an integer and vice versa. Here are some independent instruction examples\\
-''MOV X1, X0      @ X1 = X0 (64 bit register copy)''\\
+''<fc #800000>MOV</fc> <fc #008000>X1</fc>, <fc #008000>X0</fc> <fc #6495ed>@ X1 = X0 (64 bit register copy)</fc>''\\
-''MOV W1, W0      @ W1 = W0 (32 bit register copy)''\\
+''<fc #800000>MOV</fc> <fc #008000>W1</fc>, <fc #008000>W0</fc> <fc #6495ed>@ W1 = W0 (32 bit register copy)</fc>''\\
-''FMOV S1, S0     @ float → float (32-bit floating-point copy between vector registers)''\\
+''<fc #800000>FMOV</fc> <fc #008000>S1</fc>, <fc #008000>S0</fc> <fc #6495ed>@ float → float (32-bit floating-point copy between vector registers)</fc>''\\
-''FMOV X0, D1     @ FP64 → int64 (copy from vector register to general-purpose register)''\\
+''<fc #800000>FMOV</fc> <fc #008000>X0</fc>, <fc #008000>D1</fc> <fc #6495ed> @ FP64 → int64 (copy from vector register to general-purpose register)</fc>''\\
-''FMOV D2, X3     @ int64 → FP64 (copy from general-purpose register to vector register)''\\
+''<fc #800000>FMOV</fc> <fc #008000>D2</fc>, <fc #008000>X3</fc> <fc #6495ed>@ int64 → FP64 (copy from general-purpose register to vector register)</fc>''\\
-''MOV V1.16b, V0.16b	@ vector register copy one byte''\\
+''<fc #800000>MOV</fc> <fc #008000>V1</fc>.<fc #808000>16b</fc>, <fc #008000>V0</fc>.<fc #808000>16b</fc> <fc #6495ed>@ vector register copy one byte</fc>''\\
-The MOV instructions can also be used to write a value into the register immediately:\\
+The ''<fc #800000>MOV</fc>'' instructions can also be used to write a value into the register immediately. In the following example, all instructions are executed one by one:\\
-''MOV X0, #123 @ assign value 291 to the register''\\
+''<fc #800000>MOV</fc> <fc #008000>X0</fc>, <fc #ffa500>#123</fc> <fc #6495ed>@ assign value 291 to the register</fc>''\\
-''MOVZ X0, #0x1234, LSL #48 @ int64''\\
+''<fc #800000>MOVZ</fc> <fc #008000>X0</fc>, <fc #ffa500>#0x1234</fc>, <fc #800080>LSL</fc> <fc #ffa500>#48</fc><fc #6495ed> @ X0 = 0x1234 0000 0000 0000. The X0 value gets overvritten</fc>''\\
-''MOVK X0, #0xABCD, LSL #0 @ int64''\\
+''<fc #800000>MOVK</fc> <fc #008000>X0</fc>, <fc #ffa500>#0xABCD</fc>, <fc #800080>LSL</fc> <fc #ffa500>#0</fc> <fc #6495ed>@ X0 = 0x1234 0000 0000 ABCD, if before instruction execution the register value was 0x1234 0000 0000 0000</fc>''
+===== Data copy/move instructions =====
+These instructions do not work with values that require arithmetic operations. Still, they are mainly used to manipulate individual bits in registers, widely used to test or verify values, and to perform other functions. Basic logic instructions for AARCH64 are:\\
+''<fc #800000>AND</fc> <fc #008000>X0</fc>, <fc #008000>X1</fc>, <fc #008000>X2</fc> <fc #6495ed>@ logical AND between X1 and X2, result is stored in X0</fc>''\\
+''<fc #800000>ORR</fc> <fc #008000>X6</fc>, <fc #008000>X7</fc>, <fc #008000>X8</fc> <fc #6495ed>@ logical OR between X7 and X8, result is stored in X6</fc>''\\
+''<fc #800000>EOR</fc> <fc #008000>X12</fc>, <fc #008000>X13</fc>, <fc #008000>X14</fc> <fc #6495ed>@ logical XOR between X13 and X14, result is stored in X12</fc>''\\
+''<fc #800000>NEG</fc> <fc #008000>X24</fc>, <fc #008000>X25</fc> <fc #6495ed>@ logical NOT, X24 is set to inverted X25</fc>''
+Remember that most instructions, which operate with registers, can update the status register by adding the postfix S at the end of the instruction. Logical instructions are fundamental for low-level programming. These instructions allow taking control over bits and are widely used in system code, device drivers, and embedded systems. Some instructions can perform combined bitwise operations, like ''<fc #800000>ORN</fc>'', which performs an OR operation with the inverted second operand.

en/multiasm/paarm/chapter_5_6.1764797173.txt.gz · Last modified: 2025/12/03 23:26 by eriks.klavins