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| en:multiasm:paarm:chapter_5_5 [2026/02/27 11:21] – jtokarz | en:multiasm:paarm:chapter_5_5 [2026/02/27 16:17] (current) – [Other addressing modes] jtokarz | ||
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| The load and store instructions also work with 32-bit registers. Load instructions include additional options that can be used not only for data loading but also for other operations on the data in the register. For example, to load a single data byte into the register, use the ''< | The load and store instructions also work with 32-bit registers. Load instructions include additional options that can be used not only for data loading but also for other operations on the data in the register. For example, to load a single data byte into the register, use the ''< | ||
| - | {{ : | + | <figure ldrsbw0> |
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| The data are loaded from memory, and the sign bit is preserved only for a 32-bit wide value when the destination register is addressed as a 32-bit register. If the 64-bit register is used as the destination, | The data are loaded from memory, and the sign bit is preserved only for a 32-bit wide value when the destination register is addressed as a 32-bit register. If the 64-bit register is used as the destination, | ||
| - | {{ : | + | <figure ldrsbw0> |
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| Zero extension is only available for 32-bit registers because the most significant bytes are cleared when a 32-bit register is written. | Zero extension is only available for 32-bit registers because the most significant bytes are cleared when a 32-bit register is written. | ||
| - | {{ : | + | <figure ldrsbx0> |
| + | {{ : | ||
| + | < | ||
| + | </ | ||
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| ====Complex addressing modes ==== | ====Complex addressing modes ==== | ||
| This is not a real addressing mode, but some instructions allow the addressing to be a bit more complex. Loading from memory (or storing in it) data into the vector register. the LD1, LD2, LD3 and LD4 instructions loads vector register: | This is not a real addressing mode, but some instructions allow the addressing to be a bit more complex. Loading from memory (or storing in it) data into the vector register. the LD1, LD2, LD3 and LD4 instructions loads vector register: | ||
