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| en:multiasm:paarm:chapter_5_3 [2025/12/11 10:14] – [CPU Configuration] eriks.klavins | en:multiasm:paarm:chapter_5_3 [2026/05/27 09:30] (current) – [CPU Configuration] ktokarz | ||
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| The term ‘Rn’ refers to architectural registers, not the registers to be used in the assembler code. | The term ‘Rn’ refers to architectural registers, not the registers to be used in the assembler code. | ||
| - | {{ : | + | <figure registersizes> |
| + | {{ : | ||
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| Note that accessing the W0 or W1 register does not allow access to the remaining 32 most significant bits. Also, when the W register is written in a 32-bit register, the top 32 bits (most significant bits of the 64-bit register) are zeroed. And there are no registers named R0 or R1, so if we need to access the 64-bit register result, we need to address it with X0 or X1 (or other register up to X30), and similarly with 32-bit registers – W0, W1 and so on are used to address general-purpose registers. | Note that accessing the W0 or W1 register does not allow access to the remaining 32 most significant bits. Also, when the W register is written in a 32-bit register, the top 32 bits (most significant bits of the 64-bit register) are zeroed. And there are no registers named R0 or R1, so if we need to access the 64-bit register result, we need to address it with X0 or X1 (or other register up to X30), and similarly with 32-bit registers – W0, W1 and so on are used to address general-purpose registers. | ||
| These examples perform single 32-bit arithmetic operations: | These examples perform single 32-bit arithmetic operations: | ||
| - | {{ : | + | <figure arithmetic32bit> |
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| These examples perform single 64-bit arithmetic operations: | These examples perform single 64-bit arithmetic operations: | ||
| - | {{ : | + | <figure arithmetic64bit> |
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| Special registers like the Stack Pointer (SP), Link Register (LR), and Program Counter (PC) are available. The Link Register (LR) is stored in the X30 register. The Stack Pointer SP and the Program Counter PC registers are no longer available as regular general-purpose registers. It is still possible to use the SP register with a limited set of data-processing instructions via the WSP register name. Unlike ARMv7, the PC register is no longer accessible via data-processing instructions. The PC register can be read by ‘ADR’ instruction, | Special registers like the Stack Pointer (SP), Link Register (LR), and Program Counter (PC) are available. The Link Register (LR) is stored in the X30 register. The Stack Pointer SP and the Program Counter PC registers are no longer available as regular general-purpose registers. It is still possible to use the SP register with a limited set of data-processing instructions via the WSP register name. Unlike ARMv7, the PC register is no longer accessible via data-processing instructions. The PC register can be read by ‘ADR’ instruction, | ||
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| Example adding two registers together with different register notation. | Example adding two registers together with different register notation. | ||
| - | {{ : | + | <figure add64_32> |
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| ARMv8 has an additional 32 register set for floating-point and vector operations, like general-purpose registers. These registers are 128 bits wide and, like general-purpose registers, can be accessed in several ways. The letters for these registers identify byte (Bx), half-word (Hx), single-word (Sx), double-word (Dx) and quad-word (Qx) access. | ARMv8 has an additional 32 register set for floating-point and vector operations, like general-purpose registers. These registers are 128 bits wide and, like general-purpose registers, can be accessed in several ways. The letters for these registers identify byte (Bx), half-word (Hx), single-word (Sx), double-word (Dx) and quad-word (Qx) access. | ||
| - | {{ : | + | <figure vectorreg> |
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| - | {{ : | + | {{ : |
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| - | More information on these registers and operations performed with floating-point is described in the following section, “Advanced Assembly Programming”. | + | More information on these registers and operations performed with floating-point is described in the following section: [[en: |
| ===== CPU Configuration===== | ===== CPU Configuration===== | ||
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| ''< | ''< | ||
| - | {{: | + | <figure exceptionlevels> |
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| - | In the image, all of the exception levels are visualised. The Orange area is so-called the untrusted or non-secure state. The region with a blue background is the Operating System and its parts and applications. User applications can request resources using SVC (supervisor calls), or on Raspberry Pi OS (and others), this is called SysCalls. The operating system is treated as a separate program on the exception level EL1 from the EL2 perspective. If the hypervisor is available, the OS may request resources via HVC (Hypervisor calls), and the hypervisor can request resources from the secure monitor via SMC (Secure monitor calls). On Raspberry Pi 5, the bootloader runs on EL3, loading memory and initialising the hardware. Then the operating system is started at the EL1 level, and the rest of the applications in the OS are at the EL0 level. Raspberry Pi 5 does not have hypervisor software, which is why Exception Level 2 is not used. | + | In Fig. {{ref> |
| The Green region is a Secure State where only special secure applications and operating systems are executed. This may be used in system duplication, | The Green region is a Secure State where only special secure applications and operating systems are executed. This may be used in system duplication, | ||
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| You can see how many states this processor has. Not all of them are used during program execution. Many registers are related to debugging and resource management. On the Raspberry Pi, the OS and bootloader have already configured all CPU Cores and the registers. Trace registers are used only when hardware debugging is enabled, such as JTAG or TRACE32. | You can see how many states this processor has. Not all of them are used during program execution. Many registers are related to debugging and resource management. On the Raspberry Pi, the OS and bootloader have already configured all CPU Cores and the registers. Trace registers are used only when hardware debugging is enabled, such as JTAG or TRACE32. | ||
| - | Summarising: | + | Summarising: |
| - | There are rules for creating a Linux OS kernel module – it must contain functions that initialise the module and exit when the job is finished. The skeleton for the kernel module is given below in C. It will require a GCC compiler to compile the code, but inline assembly can be written directly in the code itself. After changing the Exception level from EL0 to EL1, only some system instruction executions will be allowed. | + | There are rules for creating a Linux kernel module – it must contain functions that initialise the module and exit when the job is finished. The skeleton for the kernel module is given below in C. It will require a GCC compiler to compile the code, but inline assembly can be written directly in the code itself. After changing the Exception level from EL0 to EL1, only some system instruction executions will be allowed. |
| < | < | ||
