Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| en:multiasm:paarm:chapter_5_2 [2026/02/27 15:12] – jtokarz | en:multiasm:paarm:chapter_5_2 [2026/02/27 16:26] (current) – jtokarz | ||
|---|---|---|---|
| Line 44: | Line 44: | ||
| Many instructions include options such as bit shifting. These operations also have specific instructions for binary bit shifting. These shifts affect the operand values. Shifting the register left or right by one bit multiplies or divides the value by 2, respectively. | Many instructions include options such as bit shifting. These operations also have specific instructions for binary bit shifting. These shifts affect the operand values. Shifting the register left or right by one bit multiplies or divides the value by 2, respectively. | ||
| - | {{ : | + | <figure lls> |
| - | {{ : | + | {{ : |
| - | {{ : | + | < |
| - | {{ : | + | </ |
| - | {{ : | + | |
| + | <figure lrs> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | <figure ars0> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | <figure ars1> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | <figure acs> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| **T32** | **T32** | ||
| Line 54: | Line 73: | ||
| The Thumb instructions have multiple machine codes for this one operation. | The Thumb instructions have multiple machine codes for this one operation. | ||
| - | {{ : | + | <figure t1> |
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| T1 THUMB instruction D bit and Rd fields together identify the destination register. The source and destination registers can now be addressed with only 4 bits, so only 16 general-purpose registers are accessible. A smaller number of registers can be accessed in the following machine code. | T1 THUMB instruction D bit and Rd fields together identify the destination register. The source and destination registers can now be addressed with only 4 bits, so only 16 general-purpose registers are accessible. A smaller number of registers can be accessed in the following machine code. | ||
| - | {{ : | + | <figure t2> |
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| The OP bitfield specifies the shift type, and imm5 specifies the amount. The result Rd will be shifted by imm5 bits from the Rm register. Notice that only three bits are used to address the general-purpose registers – only eight registers are accessible. | The OP bitfield specifies the shift type, and imm5 specifies the amount. The result Rd will be shifted by imm5 bits from the Rm register. Notice that only three bits are used to address the general-purpose registers – only eight registers are accessible. | ||
| Finally, the last machine code for this instruction is a sixteen 16-bit-wide instruction, | Finally, the last machine code for this instruction is a sixteen 16-bit-wide instruction, | ||
| - | {{ : | + | <figure t3> |
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| Different machine codes for the T32 instructions allow you to choose the most suitable one, but the code must be consistent with a single machine code type. Switching between machine code types in the processor is still possible, but compiling code that uses multiple machine codes will be even more complicated than learning assembler. | Different machine codes for the T32 instructions allow you to choose the most suitable one, but the code must be consistent with a single machine code type. Switching between machine code types in the processor is still possible, but compiling code that uses multiple machine codes will be even more complicated than learning assembler. | ||
