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Trace: • Evolution of the Hardware • Best Practices on Structural Programming • Optimisation • Principles of Instructions Encoding • MASM Basics • Compatibility with HLL Compilers (C++, C#) and Operating Systems • Specific Elements of the x86 and x64 Architectures • Hardware Debugging • Data Types and Encoding • Energy Efficient Programming

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en:multiasm:paarm:chapter_5_2 [2026/02/27 11:19] – jtokarzen:multiasm:paarm:chapter_5_2 [2026/02/27 16:26] (current) – jtokarz
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 **A64** **A64**
  
-The machine code for the MOV instruction is given in the figure above. The bit values presented are fixed for proper identification of the operation. The ‘sf’ bit identifies data encoding variant 32-bit (sf=0) or 64-bit(sf=1). The ‘sf’ bit does not change the instruction binary code.+The machine code for the MOV instruction is given in Fig. {{ref>mov64}}. The bit values presented are fixed for proper identification of the operation. The ‘sf’ bit identifies data encoding variant 32-bit (sf=0) or 64-bit(sf=1). The ‘sf’ bit does not change the instruction binary code.
  
-{{ :en:multiasm:paarm:mov64_32_bitform.jpg?600 |}}+<figure mov64> 
 +{{ :en:multiasm:paarm:mov64_32_bitform.jpg?600 |MMachine code for the MOV instruction in the A64 instruction set}} 
 +<caption>Machine code for the MOV instruction in the A64 instruction set</caption> 
 +</figure>
  
 The ‘Rm’ and the ‘Rd’ bit fields identify the exact register number from which the data will be copied to the destination register. Each is 5 bits wide, so all 32 CPU registers can be addressed. The ‘sf’ bit only identifies the number of bits to be copied between registers: 32 or 64 bits of data. The ‘opc’ bitfield identifies the operation variant (addressing mode for this instruction), and the ‘N’ bit, mainly used for bitwise shift operations; for others, like this one, this bit has no meaning. There are instructions where the ‘N’ bit is used to identify some instruction options, but this bit is used with the ‘imm6’ bits together. The ‘Rm’ and the ‘Rd’ bit fields identify the exact register number from which the data will be copied to the destination register. Each is 5 bits wide, so all 32 CPU registers can be addressed. The ‘sf’ bit only identifies the number of bits to be copied between registers: 32 or 64 bits of data. The ‘opc’ bitfield identifies the operation variant (addressing mode for this instruction), and the ‘N’ bit, mainly used for bitwise shift operations; for others, like this one, this bit has no meaning. There are instructions where the ‘N’ bit is used to identify some instruction options, but this bit is used with the ‘imm6’ bits together.
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 **A32** **A32**
  
-The figure above shows the same instruction, but the register address is smaller than in the A64 instruction. The bitfields ‘Rd’ and ‘Rm’ are 4-bit wide, so only 16 CPU registers can be addressed using this instruction in A32.+Fig. {{ref>mov32}} shows the same instruction, but the register address is smaller than in the A64 instruction. The bitfields ‘Rd’ and ‘Rm’ are 4-bit wide, so only 16 CPU registers can be addressed using this instruction in A32.
  
-{{ :en:multiasm:paarm:mov32_bitform.svg?600 |}}+<figure mov32> 
 +{{ :en:multiasm:paarm:mov32_bitform.svg?600 |Machine code for the MOV instruction in the A32 instruction set}} 
 +<caption>Machine code for the MOV instruction in the A32 instruction set</caption> 
 +</figure>
  
  
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 Many instructions include options such as bit shifting. These operations also have specific instructions for binary bit shifting. These shifts affect the operand values. Shifting the register left or right by one bit multiplies or divides the value by 2, respectively. Many instructions include options such as bit shifting. These operations also have specific instructions for binary bit shifting. These shifts affect the operand values. Shifting the register left or right by one bit multiplies or divides the value by 2, respectively.
  
-{{ :en:multiasm:paarm:instroptlsl.png?600 |}} +<figure lls> 
-{{ :en:multiasm:paarm:instroptlsr.png?600 |}} +{{ :en:multiasm:paarm:instroptlsl.png?600 |Logical left shift}} 
-{{ :en:multiasm:paarm:instroptasr_1.png?600 |}} +<caption>Logical left shift</caption> 
-{{ :en:multiasm:paarm:instroptasr_2.png?600 |}} +</figure> 
-{{ :en:multiasm:paarm:instroptror.png?600 |}}+ 
 +<figure lrs> 
 +{{ :en:multiasm:paarm:instroptlsr.png?600 |Logical right shift}} 
 +<caption>Logical right shift</caption> 
 +</figure> 
 + 
 +<figure ars0> 
 +{{ :en:multiasm:paarm:instroptasr_1.png?600 |Arithmetic right shift with MSB equal to 0}} 
 +<caption>Arithmetic right shift with MSB equal to 0</caption> 
 +</figure> 
 + 
 +<figure ars1> 
 +{{ :en:multiasm:paarm:instroptasr_2.png?600 |Arithmetic right shift with MSB equal to 1}} 
 +<caption>Arithmetic right shift with MSB equal to 1</caption> 
 +</figure> 
 + 
 +<figure acs> 
 +{{ :en:multiasm:paarm:instroptror.png?600 |Right circular shift}} 
 +<caption>Right circular shift</caption> 
 +</figure>
  
 **T32** **T32**
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 The Thumb instructions have multiple machine codes for this one operation.  The Thumb instructions have multiple machine codes for this one operation. 
  
-{{ :en:multiasm:paarm:thumbt1.svg?600 |}}+<figure t1> 
 +{{ :en:multiasm:paarm:thumbt1.svg?600 |T1 THUMB instruction}} 
 +<caption>T1 THUMB instruction</caption> 
 +</figure>
  
 T1 THUMB instruction D bit and Rd fields together identify the destination register. The source and destination registers can now be addressed with only 4 bits, so only 16 general-purpose registers are accessible. A smaller number of registers can be accessed in the following machine code. T1 THUMB instruction D bit and Rd fields together identify the destination register. The source and destination registers can now be addressed with only 4 bits, so only 16 general-purpose registers are accessible. A smaller number of registers can be accessed in the following machine code.
  
-{{ :en:multiasm:paarm:thumbt2.svg?600 |}}+<figure t2> 
 +{{ :en:multiasm:paarm:thumbt2.svg?600 |T2 THUMB instruction}} 
 +<caption>T2 THUMB instruction</caption> 
 +</figure>
  
 The OP bitfield specifies the shift type, and imm5 specifies the amount. The result Rd will be shifted by imm5 bits from the Rm register. Notice that only three bits are used to address the general-purpose registers – only eight registers are accessible. The OP bitfield specifies the shift type, and imm5 specifies the amount. The result Rd will be shifted by imm5 bits from the Rm register. Notice that only three bits are used to address the general-purpose registers – only eight registers are accessible.
 Finally, the last machine code for this instruction is a sixteen 16-bit-wide instruction, but the Rd and Rm fields are still 4 bits wide. This instruction provides more shift operations than the previous one, but instead of a single imm5 field specifying the shift amount, it is split into two fields: imm3 and imm2. Both parts are combined for the same purpose: to identify the shift amount. Finally, the last machine code for this instruction is a sixteen 16-bit-wide instruction, but the Rd and Rm fields are still 4 bits wide. This instruction provides more shift operations than the previous one, but instead of a single imm5 field specifying the shift amount, it is split into two fields: imm3 and imm2. Both parts are combined for the same purpose: to identify the shift amount.
  
-{{ :en:multiasm:paarm:thumbt3.svg?600 |}}+<figure t3> 
 +{{ :en:multiasm:paarm:thumbt3.svg?600 |T3 THUMB instruction}} 
 +<caption>T3 THUMB instruction</caption> 
 +</figure>
  
 Different machine codes for the T32 instructions allow you to choose the most suitable one, but the code must be consistent with a single machine code type. Switching between machine code types in the processor is still possible, but compiling code that uses multiple machine codes will be even more complicated than learning assembler.  Different machine codes for the T32 instructions allow you to choose the most suitable one, but the code must be consistent with a single machine code type. Switching between machine code types in the processor is still possible, but compiling code that uses multiple machine codes will be even more complicated than learning assembler. 
en/multiasm/paarm/chapter_5_2.1772183962.txt.gz · Last modified: by jtokarz
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