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| en:multiasm:paarm:chapter_5_2 [2026/06/21 15:32] – pczekalski | en:multiasm:paarm:chapter_5_2 [2026/06/21 15:37] (current) – pczekalski |
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| ====== ARM Assembly Language Specifics ====== | ====== ARM Assembly Language Specifics ====== |
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| Before starting programming, it's good to know how to add comments to our newly created code and the specifics of the syntax. This mainly depends on the selected compiler. All code examples provided will be written in GNU ARM ASM. { https://sourceware.org/binutils/docs-2.26/as/} | Before starting programming, it's good to know how to add comments to our newly created code and the specifics of the syntax. This mainly depends on the selected compiler. All code examples provided will be written in GNU ARM ASM { https://sourceware.org/binutils/docs-2.26/as/}.\\ |
| The symbol ‘@’ is used to create a comment in the code till the end of the exact line. Some other assembly languages use ‘;’ to comment, but in ARM assembly language, ‘;’ indicates a new line to separate statements. The suggestion is to avoid the use of this ‘;’ character; there will be no such statements that would be divided into separate code lines. Multiline comments are created in the same way as in C/C++ programming languages by use of ‘/*’ and ‘*/’ character combinations. However, it is better to read the manual and the syntax for each piece of software used to create and compile the code. | The symbol' @' is used to create a comment in the code till the end of the exact line. Some other assembly languages use ';' to comment, but in ARM assembly language, ';' indicates a new line to separate statements. The suggestion is to avoid using the ';' character; there will be no statements that need to be split across separate code lines. Multiline comments are created in the same way as in C/C++ programming languages by use of '/*' and '*/' character combinations. However, it is better to read the manual and the syntax for each piece of software used to create and compile the code. |
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| Now, let's compare the Cortex-M and Cortex-A series. The ARMv8-A processor series supports three instruction sets: A32, T32, and A64. A32 and T32 are the Arm and Thumb instruction sets, respectively. These instruction sets are used to execute instructions in the AArch32 Execution state. The A64 instruction set is used when executing in the AArch64 Execution state, and there are no 64-bit-wide instructions; it does not refer to instruction size in memory. | Now, let's compare the Cortex-M and Cortex-A series. The ARMv8-A processor series supports three instruction sets: A32, T32, and A64.\\ A32 and T32 are the ARM and Thumb instruction sets, respectively. These instruction sets are used to execute instructions in the AArch32 Execution state. The A64 instruction set is used when executing in the AArch64 Execution state, and there are no 64-bit-wide instructions; it does not refer to instruction size in memory.\\ |
| ARM Cortex-M processors based on ARMv7 can execute two instruction sets: Thumb and ARM. The Thumb instructions are 16-bit wide and have some restrictions, such as access to registers. Many microcontrollers currently use the ARMv7 processor, but new ones based on ARMv8 and ARMv8.1 are already available. The ARMv8-M series processors support only Thumb instructions; there is no ARM state to execute ARM32 instructions, so these processors do not support the A32 instruction set. The feature was removed, maybe because there was no need to use the ARM state – many compilers use the Thumb instruction set. | ARM Cortex-M processors based on ARMv7 can execute two instruction sets: Thumb and ARM.\\ The Thumb instructions are 16-bit wide and have some restrictions, such as access to registers. Many microcontrollers currently use the ARMv7 processor, but new ones based on ARMv8 and ARMv8.1 are already available. The ARMv8-M series processors support only Thumb instructions; there is no ARM state to execute ARM32 instructions, so these processors do not support the A32 instruction set. The feature was removed, maybe because there was no need to use the ARM state – many compilers use the Thumb instruction set. |
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| Looking at the ARMv8-A processors, the instruction sets make a difference. AArch32 execution state can execute programs designed for ARMv7 processors. This means many A32 or T32 instructions on ARMv8 are identical to the ARMv7 ARM or THUMB instructions, respectively. On ARMv7 processors, the THUMB instruction set has some restrictions, such as reduced access to general-purpose registers, whereas the ARM instruction set provides complete access to all registers. Similar access restrictions are also found on ARMv8 processors. | Looking at the ARMv8-A processors, the instruction sets make a difference. AArch32 execution state can execute programs designed for ARMv7 processors. This means many A32 or T32 instructions on ARMv8 are identical to those on the ARMv7 ARM or THUMB instructions, respectively. On ARMv7 processors, the THUMB instruction set has some restrictions, such as reduced access to general-purpose registers, whereas the ARM instruction set provides complete access to all registers. Similar access restrictions are also found on ARMv8 processors.\\ |
| Let's look at the machine code generated by the assembler to determine why the exact instruction set imposes restrictions on the ARMv8 processor. We will take just one instruction, one of the most common, the MOV instruction. Multiple machine code variants for the MOV instruction are generated due to different addressing modes. We will take just one instruction that copies a value from one register to another. All information on the machine code is available on the ARM homepage: for A64, the documentation number is DDI0602. | Let's look at the machine code generated by the assembler to determine why the exact instruction set imposes restrictions on the ARMv8 processor. We will take just one instruction, one of the most common, the MOV instruction. Multiple machine code variants for the MOV instruction are generated due to different addressing modes. We will take just one instruction that copies a value from one register to another. All information on the machine code is available on the ARM homepage: for A64, the documentation number is DDI0602. |
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| **A64** | **A64** |
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| The machine code for the MOV instruction is given in Fig. {{ref>mov64}}. The bit values presented are fixed for proper identification of the operation. The ‘sf’ bit identifies data encoding variant 32-bit (sf=0) or 64-bit(sf=1). The ‘sf’ bit does not change the instruction binary code. | The machine code for the MOV instruction is given in Fig. {{ref>mov64}}. The bit values presented are fixed for proper identification of the operation. The 'sf' bit identifies the data encoding variant: 32-bit (''sf=0'') or 64-bit (''sf=1''). The 'sf' bit does not change the instruction binary code. |
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| <figure mov64> | <figure mov64> |
| </figure> | </figure> |
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| The ‘Rm’ and the ‘Rd’ bit fields identify the exact register number from which the data will be copied to the destination register. Each is 5 bits wide, so all 32 CPU registers can be addressed. The ‘sf’ bit only identifies the number of bits to be copied between registers: 32 or 64 bits of data. The ‘opc’ bitfield identifies the operation variant (addressing mode for this instruction), and the ‘N’ bit, mainly used for bitwise shift operations; for others, like this one, this bit has no meaning. There are instructions where the ‘N’ bit is used to identify some instruction options, but this bit is used with the ‘imm6’ bits together. | The 'Rm' and the 'Rd' bit fields identify the exact register number from which the data will be copied to the destination register. Each is 5 bits wide, so all 32 CPU registers can be addressed. The 'sf' bit only specifies the number of bits to be copied between registers: 32 or 64 bits. The 'opc' bitfield identifies the operation variant (addressing mode for this instruction), and the 'N' bit, mainly used for bitwise shift operations; for others, like this one, this bit has no meaning. There are instructions where the 'N' bit is used to identify some instruction options, but this bit is used with the 'imm6' bits together. |
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| **A32** | **A32** |
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| Fig. {{ref>mov32}} shows the same instruction, but the register address is smaller than in the A64 instruction. The bitfields ‘Rd’ and ‘Rm’ are 4-bit wide, so only 16 CPU registers can be addressed using this instruction in A32. | Fig. {{ref>mov32}} shows the same instruction, but the register address is smaller than in the A64 instruction. The bitfields' Rd' and 'Rm' are 4-bit wide, so only 16 CPU registers can be addressed using this instruction in A32. |
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| <figure mov32> | <figure mov32> |
| </figure> | </figure> |
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| | Other bitfields, like 'cond', are also used for conditional instruction execution. The 'S' bit identifies whether the status register must be updated. The 'stype' bitfield is used for the type of shift to be applied to the second source register, and finally, the 'imm5' bitfield is used to identify the shift amount 0 to 31. |
| Other bitfields, like ‘cond’, are also used for conditional instruction execution. The ‘S’ bit identifies whether the status register must be updated. The ’stype’ bitfield is used for the type of shift to be applied to the second source register, and finally, the ‘imm5’ bitfield is used to identify the shift amount 0 to 31. | |
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| <table tab_label> | <table tab_label> |
| </figure> | </figure> |
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| T1 THUMB instruction D bit and Rd fields together identify the destination register. The source and destination registers can now be addressed with only 4 bits, so only 16 general-purpose registers are accessible. Fewer registers can be accessed in the following machine code. | T1 THUMB instruction 'D' bit and 'Rd' fields together identify the destination register. The source and destination registers can now be addressed with only 4 bits, so only 16 general-purpose registers are accessible. Fewer registers are available in the following machine code. |
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| <figure t2> | <figure t2> |
| </figure> | </figure> |
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| The OP bitfield specifies the shift type, and imm5 specifies the amount. The result Rd will be shifted by imm5 bits from the Rm register. Notice that only three bits are used to address the general-purpose registers – only eight registers are accessible. | The 'OP' bitfield specifies the shift type, and imm5 specifies the amount. The result 'Rd' will be shifted by 'imm5' bits from the 'Rm' register. Notice that only three bits are used to address the general-purpose registers – only eight registers are accessible. |
| Finally, the last machine code for this instruction is a sixteen 16-bit-wide instruction, but the Rd and Rm fields are still 4 bits wide. This instruction provides more shift operations than the previous one, but instead of a single imm5 field specifying the shift amount, the shift amount is split into two fields: imm3 and imm2. Both parts are combined for the same purpose: to determine the amount of the shift. | Finally, the last machine code for this instruction is a sixteen 16-bit-wide instruction, but the 'Rd' and 'Rm' fields are still 4 bits wide. This instruction provides more shift operations than the previous one, but instead of a single 'imm5' field specifying the shift amount, the shift amount is split into two fields: 'imm3' and 'imm2'. Both parts are combined for the same purpose: to determine the amount of the shift. |
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| <figure t3> | <figure t3> |
