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| en:multiasm:paarm:chapter_5_12 [2025/12/08 12:33] – eriks.klavins | en:multiasm:paarm:chapter_5_12 [2026/02/27 16:55] (current) – [Conditional instructions] jtokarz |
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| ''<fc #800000>ADD </fc> <fc #008000>X1</fc>, <fc #008000>X1</fc>, <fc #ffa500>#1</fc> <fc #6495ed>@ This executes speculatively while B.EQ remains unresolved</fc>''\\ | ''<fc #800000>ADD </fc> <fc #008000>X1</fc>, <fc #008000>X1</fc>, <fc #ffa500>#1</fc> <fc #6495ed>@ This executes speculatively while B.EQ remains unresolved</fc>''\\ |
| The possible outcomes are shown in the picture below. | The possible outcomes are shown in the picture below. |
| {{:en:multiasm:paarm:spec_cmp.jpg|}} | <figure cmp> |
| | {{ :en:multiasm:paarm:spec_cmp.jpg?600 |CMP instruction outcomes}} |
| | <caption>CMP instruction outcomes</caption> |
| | </figure> |
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| In the example above, the comparison is made on the ''<fc #008000>X0</fc>'' register. The next instruction creates a branch to the label. In the pipeline, while ''<fc #800000>B</fc>.<fc #9400d3>EQ </fc>'' instruction is being executed; the next instruction is already prepared to be executed, if not already (by speculation). When the branch outcome becomes known, the pipeline either commits the results (if the prediction was correct) or flushes the pipeline and re-fetches from the correct address (if the prediction was wrong). In such a way, if the register is not equal to zero, processor speculation wins in performance; otherwise, the third instruction result is discarded, and any microoperation for this instruction is cancelled—the processor branches to a new location. | In the example above, the comparison is made on the ''<fc #008000>X0</fc>'' register. The next instruction creates a branch to the label. In the pipeline, while ''<fc #800000>B</fc>.<fc #9400d3>EQ </fc>'' instruction is being executed; the next instruction is already prepared to be executed, if not already (by speculation). When the branch outcome becomes known, the pipeline either commits the results (if the prediction was correct) or flushes the pipeline and re-fetches from the correct address (if the prediction was wrong). In such a way, if the register is not equal to zero, processor speculation wins in performance; otherwise, the third instruction result is discarded, and any microoperation for this instruction is cancelled—the processor branches to a new location. |
| Other conditional instructions can be used similarly: | Other conditional instructions can be used similarly: |
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| {{:en:multiasm:paarm:conditionainst.jpg|}} | <figure conditionainst> |
| | {{ :en:multiasm:paarm:conditionainst.jpg?600 |Examples of other conditional instructions' use}} |
| | <caption>Examples of other conditional instructions' use</caption> |
| | </figure> |
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| These conditional instructions are helpful in branchless conditional checks. Taking into account that these instructions can also be executed speculatively, this execution won't waste power compared to branching if branch prediction fails. | These conditional instructions are helpful in branchless conditional checks. Taking into account that these instructions can also be executed speculatively, this execution won't waste power compared to branching if branch prediction fails. |
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