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en:multiasm:cs:chapter_3_9 [2026/06/23 13:30] – [Pipeline] pczekalskien:multiasm:cs:chapter_3_9 [2026/06/23 13:32] (current) – [Superscalar] pczekalski
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 <figure superscalar> <figure superscalar>
 {{ :en:multiasm:cs:superscalar.png?600 |Superscalar architecture of pipelined processor}} {{ :en:multiasm:cs:superscalar.png?600 |Superscalar architecture of pipelined processor}}
-<caption>Superscalar architecture of pipelined processor</caption>+<caption>Superscalar Architecture of Pipelined Processor</caption>
 </figure> </figure>
 In the x86 family, the first processor with two execution paths was the Pentium, which had two execution units, U and V. Modern x64 processors, such as the Intel i7, implement six execution units. Not all execution units have the same functionality. For example, in the i7 processor, each execution unit has different capabilities, as shown in table {{ref>executionunits}}. In the x86 family, the first processor with two execution paths was the Pentium, which had two execution units, U and V. Modern x64 processors, such as the Intel i7, implement six execution units. Not all execution units have the same functionality. For example, in the i7 processor, each execution unit has different capabilities, as shown in table {{ref>executionunits}}.
en/multiasm/cs/chapter_3_9.txt · Last modified: by pczekalski
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