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| en:multiasm:cs:chapter_3_5 [2026/01/10 10:01] – pczekalski | en:multiasm:cs:chapter_3_5 [2026/02/27 14:24] (current) – old revision restored (2026/02/24 10:19) jtokarz | ||
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| - | ====== Processor Taxonomies, SISD, SIMD, MIMD ====== | + | ====== Processor Taxonomies, SISD, SIMD, MIMD, MISD, SIMT ====== |
| As we already know, the processor executes instructions that process data. We can consider two streams flowing through the processor. A stream of instructions which passes through the control unit, and a stream of data processed by the execution unit. In 1966, Michael Flynn proposed the taxonomies to define different processors' | As we already know, the processor executes instructions that process data. We can consider two streams flowing through the processor. A stream of instructions which passes through the control unit, and a stream of data processed by the execution unit. In 1966, Michael Flynn proposed the taxonomies to define different processors' | ||
| Taxonomies as proposed by Flynn are presented in Table{{ref> | Taxonomies as proposed by Flynn are presented in Table{{ref> | ||
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| ===== MIMD ===== | ===== MIMD ===== | ||
| - | Multiple Instruction Multiple Data is an architecture in which many control units operate on multiple data streams. These are all architectures with more than one processor (multi-processor architectures). MIMD architectures include multi-core processors | + | Multiple Instruction Multiple Data is an architecture in which many control units operate on multiple data streams. These are all architectures with more than one processor (multi-processor architectures). MIMD architectures include multi-core processors |
| ===== MISD ===== | ===== MISD ===== | ||
| - | Multiple Instruction Single Data. At first glance, it seems illogical, but in these machines, the certainty of correct calculations is crucial | + | Multiple Instruction Single Data. At first glance, it seems illogical, but in these machines, the certainty of correct calculations is crucial |
| ===== SIMT ===== | ===== SIMT ===== | ||
