Components of Processor: Registers, ALU, Bus Control, Instruction Decoder

From our perspective, the processor is the electronic integrated circuit that controls other elements of the computer. Its main ability is to execute instructions. While we will go into details of the instruction set, you will see that some instructions perform calculations or process data, while others do not. This suggests that the processor comprises two main units. One of them is responsible for instruction execution, while the second performs data processing. The first one is called the control unit or instruction processor. The second one is named the execution unit or data processor. We can see them in Fig 1.

The function of the control unit, also known as the instruction processor, is to fetch, decode and execute instructions. It also generates signals to the execution unit if the instruction being executed requires it. It is a synchronous and sequential unit. Synchronous means it changes state in step with the clock signal. Sequential means that the next state depends on the input states and the current internal state. As inputs, we can consider not only physical signals from other units of the computer but also the instruction code. To ensure that the computer behaves consistently every time it is powered on, the execution unit is reset to a known state at the start of operation by the RESET signal. A typical control unit contains some essential elements:

• Instruction register (IR).
• Instruction decoder.
• Program counter (PC)/instruction pointer (IP).
• Stack pointer (SP).
• Bus interface unit.
• Interrupt controller.

Elements of the control unit are shown in Fig 2.

The control unit executes instructions in a few steps:

• Generates the address of the instruction.
• Fetches instruction code from memory.
• Decodes instructions.
• Generates signals to the execution unit or executes instructions internally.

In detail, the process looks as follows:

1. The control unit takes the address of the instruction to be executed from a special register known as the Instruction Pointer or Program Counter and sends it to the memory via the address bus. It also generates signals on the control bus to synchronise memory with the processor.
2. Memory takes the code of instruction from the provided address and sends it to the processor using a data bus.
3. The processor stores the instruction code in the instruction register and, based on the bit pattern, interprets what to do next.
4. If the instruction requires the execution unit operation, the control unit generates signals to control it. In cooperation with the execution unit, it can also read from or write to memory.

The control unit operates according to the clock signal generator's cycles, known as main clock cycles. With every clock cycle, some internal operations are performed. One such operation is reading or writing the memory, which sometimes requires more than a single clock cycle. Single memory access is known as a machine cycle. Because instruction execution sometimes requires multiple memory accesses and other actions, the execution of the whole instruction is called an instruction cycle. In summary, one instruction execution requires one instruction cycle and several machine cycles, each consisting of a few main clock cycles. Modern processors are designed to execute a single instruction (sometimes more than one) every clock cycle. This requires a more complex control unit design, multiple execution units, and other advanced techniques that enable processing more than one instruction at a time.

The control unit also accepts input signals from peripherals, enabling interrupts and direct memory access mechanisms. For proper return from the interrupt subroutine, the control unit uses a special register called the stack pointer. Interrupts and direct memory access mechanisms will be explained in detail in further chapters.

An execution unit, also known as the data processor, executes instructions. Typically, it is composed of a few essential elements:

• Arithmetic logic unit (ALU).
• Accumulator and set of registers,
• Flags register,
• Temporal register.

The arithmetic logic unit (ALU) is the element that performs both logical and arithmetic operations. It uses data from registers, the accumulator, or memory. Data coming from memory for arithmetic and logic instructions is stored in the temporal register. The result of calculations is stored back in the accumulator, another register or memory. In some legacy CISC processors, the only place to store the result is the accumulator. In addition to the result, the ALU returns additional information about the calculations. It modifies the bits in the flag register, which contains flags updated by the results of arithmetic and logical operations. For example, if the result of the addition operation is too large to be stored in the resulting argument, the carry flag is set to indicate such a situation.

Typically, the flags register includes:

• Carry flag, set in case a carry or borrow occurs.
• Sign flag, indicating whether the result is negative.
• Zero flag, set in case the result is zero.
• Auxiliary Carry flag used in BCD operations.
• Parity flag, which indicates whether the result has an even number of ones.

The flags are used as conditions for decision-making instructions (like if statements in some high-level languages). The flags register can also store control flags to enable/disable processor functionality. An example of such a flag is the Interrupt Enable flag on the 8086 microprocessor.

Registers are memory elements that are placed very close to the arithmetic logic unit, both logically and physically. It makes them the fastest memory in the whole computer. They are sometimes called scratch registers, and the set of registers is called the register file.

As we mentioned in the chapter on CISC and RISC processors, CISC processors have specialised registers, including the accumulator. A typical CISC execution unit is shown in Fig 3.

A typical RISC execution unit does not have a specialised accumulator register. It implements the set of scratch registers as shown in Fig 4.