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en:multiasm:cs:chapter_3_3 [2026/02/27 14:10] – [Table] jtokarzen:multiasm:cs:chapter_3_3 [2026/02/27 14:24] (current) – old revision restored (2026/01/10 09:58) jtokarz
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 <table ciscrisc> <table ciscrisc>
 <caption>CISC and RISC features</caption> <caption>CISC and RISC features</caption>
-<fs small>Feature</fs>                      <fs small>CISC</fs>              <fs small>RISC</fs>               ^ +^ Feature                      ^ CISC              ^ RISC               ^ 
-<fs small>Instructions</fs>                 | <fs small>Complex</fs>           | <fs small>Simple</fs>             | +| Instructions                 | Complex           | Simple             | 
-<fs small>Registers</fs>                    <fs small>Specialised</fs>       | <fs small>Universal</fs>          | +| Registers                    | Specialised       | Universal          | 
-<fs small>Number of registers</fs>          <fs small>Smaller</fs>           | <fs small>Larger</fs>             | +| Number of registers          | Smaller           | Larger             | 
-<fs small>Calculations</fs>                 | <fs small>With accumulator</fs>  <fs small>With any register</fs>  | +| Calculations                 | With accumulator  | With any register 
-<fs small>Addressing modes</fs>             | <fs small>Complex</fs>           | <fs small>Simple</fs>             | +| Addressing modes             | Complex           | Simple             | 
-<fs small>Non destroying instructions</fs>  <fs small>No</fs>                <fs small>Yes</fs>                | +| Non destroying instructions  | No                | Yes                | 
-<fs small>Examples of processors</fs>       | <fs small>8086, 8051</fs>        <fs small>AVR, ARM</fs>           |+| Examples of processors       | 8086, 8051        | AVR, ARM           |
 </table> </table>
  
 These features make the RISC architecture more flexible, allowing programmers or compilers to write code without unnecessary data transfers. The execution units of RISC processors can be simpler in construction, enabling higher operating frequencies and faster program execution. What is interesting is that the modern versions of popular CISC machines, such as Intel and AMD processors used in personal computers, internally translate CISC instructions into RISC microoperations, which are executed by execution units. These features make the RISC architecture more flexible, allowing programmers or compilers to write code without unnecessary data transfers. The execution units of RISC processors can be simpler in construction, enabling higher operating frequencies and faster program execution. What is interesting is that the modern versions of popular CISC machines, such as Intel and AMD processors used in personal computers, internally translate CISC instructions into RISC microoperations, which are executed by execution units.
 A simple instruction can be converted directly into a single microoperation. Complex instructions are often implemented as sequences of microoperations called microcodes. A simple instruction can be converted directly into a single microoperation. Complex instructions are often implemented as sequences of microoperations called microcodes.
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