Von Neumann vs Harvard Architectures, Mixed Architectures

The classical architecture of computers uses a single address and a single data bus to connect the processor, memory and peripherals. This architecture is called the von Neumann, or Princeton, architecture, and we show it in Fig. 1. Additionally, in this architecture, memory contains program code and the data they use. Because it shares the same set of buses for program and data, it suffers from the drawback of not being able to access the program's instructions and the data simultaneously, a limitation known as the von Neumann bottleneck. The answer to this issue is the Harvard architecture, in which program memory is separated from data memory, and they are connected to the processor via two pairs of address and data buses. Of course, the processor must support such an architecture. The Harvard architecture we show in Fig. 2.

Harvard architecture is very often used in one-chip computers. It does not suffer from the von Neumann bottleneck and additionally allows implementing different data-word and instruction-word lengths. For example, the AVR 8-bit microcontroller family has a 16-bit program word. PIC microcontrollers, also in the 8-bit class, have 13- or 14-bit instruction word lengths. In modern microcontrollers, the program is usually stored in internal flash reprogrammable memory, and data in internal static RAM memory. All interconnections, including address and data buses, are implemented internally, making the Harvard architecture easier to implement than in a microprocessor-based computer. In several mature microcontrollers, the program and data memories are separate but connected to the processor unit via a single set of buses. It is named mixed architecture. This architecture benefits from an enlargement of the size of the possible address space, but still suffers from the von Neumann bottleneck. This approach can be found in the 8051 microcontroller family. The schematic diagram of mixed architecture we presented in Fig. 3.