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| **Control bus** is formed by lines mainly used for synchronisation between the elements of the computer. The minimal implementation includes the read and write lines. Read line (#RD) is the information that other elements use to indicate that the processor wants to read data from the unit. In such a situation, the element, e.g. memory, puts the data from the addressed cell on the data bus. Active write signal (#WR) informs the element that the data which is present on the data bus should be stored at the specified address. | **Control bus** is formed by lines mainly used for synchronisation between the elements of the computer. The minimal implementation includes the read and write lines. Read line (#RD) is the information that other elements use to indicate that the processor wants to read data from the unit. In such a situation, the element, e.g. memory, puts the data from the addressed cell on the data bus. Active write signal (#WR) informs the element that the data which is present on the data bus should be stored at the specified address. | ||
| The control bus can also include other signals specific to the system, e.g., interrupt signals, DMA control lines, clock pulses, signals distinguishing memory and peripheral access, signals activating selected modules, and others. | The control bus can also include other signals specific to the system, e.g., interrupt signals, DMA control lines, clock pulses, signals distinguishing memory and peripheral access, signals activating selected modules, and others. | ||
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