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Trace: • Overall View on Computer Architecture: Processor, Memory, I/O, Buses • Interruptores • Processor Taxonomies, SISD, SIMD, MIMD, MISD, SIMT

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en:multiasm:cs:chapter_3_1 [2026/01/10 20:09] – pczekalskien:multiasm:cs:chapter_3_1 [2026/03/01 14:00] (current) – [Buses] ktokarz
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-====== Overall View on Computer Architecture: Processor, Memory, IO, Buses ======+====== Overall View on Computer Architecture: Processor, Memory, I/O, Buses ======
 The computers we use every day are all designed around the same general idea of cooperation among three base elements: processor, memory and peripheral devices. Their names represent their functions in the system: memory stores data and program code, the processor manipulates data by executing programs, and peripherals maintain contact with the user, the environment and other systems. To exchange information, these elements communicate through interconnections named buses. The generic block schematic diagram of the exemplary computer is shown in Fig. {{ref>compblock}}. The computers we use every day are all designed around the same general idea of cooperation among three base elements: processor, memory and peripheral devices. Their names represent their functions in the system: memory stores data and program code, the processor manipulates data by executing programs, and peripherals maintain contact with the user, the environment and other systems. To exchange information, these elements communicate through interconnections named buses. The generic block schematic diagram of the exemplary computer is shown in Fig. {{ref>compblock}}.
  
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 ===== Processor ===== ===== Processor =====
-It is often called “the brain” of the computer. Although it doesn’t think, the processor is the element which controls all other units of the computer. The processor is the device that manages everything in the machine. Every hardware component of the computer is controlled, to some extent, by the main processor. Even if the device has its own processor - for example, a keyboard - it works under the control of the main one. The processor handles events. We can say that synchronous events are those that the processor handles periodically. The processor can’t stop. Of course, when it has the power, even when you don’t see anything special happening on the screen. On a PC with an operating system without a graphical user interface, for example, plain Linux, or in a command box in Windows, if you see only „C:\>”, the processor is working. In this situation, it executes the system's main loop. In such a loop, it’s waiting for the asynchronous events. Such an asynchronous event occurs when the user presses a key or moves the mouse, when the sound card stops playing a sound, or when the hard disk begins transmitting data. For all of those actions, the processor handles executing the programs - or, if you prefer, procedures.+It is often called “the brain” of the computer. Although it doesn’t think, the processor is the element which controls all other units of the computer. The processor is the device that manages everything in the machine. Every hardware component of the computer is controlled, to some extent, by the main processor. Even if the device has its own processor - for example, a keyboard - it works under the control of the main one. The processor handles events, which can be synchronous or asynchronous. We can say that synchronous events are those that the processor handles periodically. The processor can’t stop. Of course, when it has the power. Even when you don’t see anything special happening on the screen. On a PC with an operating system without a graphical user interface, for example, plain Linux, or in a command box in Windows, if you see only „C:\>”, the processor is working. In this situation, it executes the system's main loop. In such a loop, it’s waiting for the asynchronous events. Such an asynchronous event occurs when the user presses a key or moves the mouse, when the sound card stops playing a sound, or when the hard disk begins transmitting data. For all of those actions, the processor handles executing the programs - or, in other words, procedures.
  
 A processor is characterised by its main parameters, including its operating frequency and class. A processor is characterised by its main parameters, including its operating frequency and class.
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 <note info> The byte is historically assumed to be 8 bits of information and used as the base unit to express the size of data in the world of computers. </note> <note info> The byte is historically assumed to be 8 bits of information and used as the base unit to express the size of data in the world of computers. </note>
 The size of the memory installed on the computer does not have to match the size of the address space, the maximum size of memory which is addressable by the processor. In modern machines, it would be impossible or hardly achievable. For example, for x64 architecture, the theoretical address space is 2^64 (16 exabytes). Even the address space currently supported by processors' hardware is as large as 2^48, which equals 256 terabytes. On the opposite side, in constrained devices, the physical memory size can exceed what the processor supports. To enable access to memory beyond the processor's addressing space or to support flexible placement of programs in a large address space, the paging mechanism is used. It is a hardware support unit that maps the processor's address into the physical memory installed in the computer.  The size of the memory installed on the computer does not have to match the size of the address space, the maximum size of memory which is addressable by the processor. In modern machines, it would be impossible or hardly achievable. For example, for x64 architecture, the theoretical address space is 2^64 (16 exabytes). Even the address space currently supported by processors' hardware is as large as 2^48, which equals 256 terabytes. On the opposite side, in constrained devices, the physical memory size can exceed what the processor supports. To enable access to memory beyond the processor's addressing space or to support flexible placement of programs in a large address space, the paging mechanism is used. It is a hardware support unit that maps the processor's address into the physical memory installed in the computer. 
-<note info> To learn more about paging please refer to https://connormcgarr.github.io/paging/ </note>+<note info>To learn more about paging, please refer to the website 
 +https://connormcgarr.github.io/paging/</note>
  
 ===== Peripherals ===== ===== Peripherals =====
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 **Address bus** delivers the address generated by the processor to memory or peripherals. This address specifies the single memory cell or peripheral register that the processor wants to access. The address bus is used not only to address the data which the processor wants to transmit to or from memory or a peripheral. Instructions are also stored in memory, so the address bus also selects the instruction that the processor fetches and later executes. The address bus is one-directional. The address is generated by the processor and delivered to other units.  **Address bus** delivers the address generated by the processor to memory or peripherals. This address specifies the single memory cell or peripheral register that the processor wants to access. The address bus is used not only to address the data which the processor wants to transmit to or from memory or a peripheral. Instructions are also stored in memory, so the address bus also selects the instruction that the processor fetches and later executes. The address bus is one-directional. The address is generated by the processor and delivered to other units. 
 <note info> If there is a DMA controller in the computer, in some circumstances, it can also generate an address instead of the processor. Refer to the chapter that describes the DMA. </note> <note info> If there is a DMA controller in the computer, in some circumstances, it can also generate an address instead of the processor. Refer to the chapter that describes the DMA. </note>
-The number of lines in the address bus is fixed for the processor and determines the size of the addressing space the processor can access. For example, if the address bus of some processor has 16 lines, it can generate up to 16^2 = 65536 different addresses.+The number of lines in the address bus is fixed for the processor and determines the size of the addressing space the processor can access. For example, if the address bus of some processor has 16 lines, it can generate up to 2^16 = 65536 different addresses.
  
 **Data bus** is used to exchange data between the processor and the memory or peripherals. The processor can read data from memory or peripherals, or write data to these units, previously sending their addresses on the address bus. As data can be read or written, the data bus is bi-directional. **Data bus** is used to exchange data between the processor and the memory or peripherals. The processor can read data from memory or peripherals, or write data to these units, previously sending their addresses on the address bus. As data can be read or written, the data bus is bi-directional.
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 **Control bus** is formed by lines mainly used for synchronisation between the elements of the computer. The minimal implementation includes the read and write lines. Read line (#RD) is the information that other elements use to indicate that the processor wants to read data from the unit. In such a situation, the element, e.g. memory, puts the data from the addressed cell on the data bus. Active write signal (#WR) informs the element that the data which is present on the data bus should be stored at the specified address. **Control bus** is formed by lines mainly used for synchronisation between the elements of the computer. The minimal implementation includes the read and write lines. Read line (#RD) is the information that other elements use to indicate that the processor wants to read data from the unit. In such a situation, the element, e.g. memory, puts the data from the addressed cell on the data bus. Active write signal (#WR) informs the element that the data which is present on the data bus should be stored at the specified address.
 The control bus can also include other signals specific to the system, e.g., interrupt signals, DMA control lines, clock pulses, signals distinguishing memory and peripheral access, signals activating selected modules, and others. The control bus can also include other signals specific to the system, e.g., interrupt signals, DMA control lines, clock pulses, signals distinguishing memory and peripheral access, signals activating selected modules, and others.
 +
 +<note info>
 +The "#" symbol before a signal name means that the active signal on the line is a LOW state, while idle is a HIGH state.
 +</note>
  
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