https://home.roboticlab.eu/ 2026-04-04T16:50:05+00:00 https://home.roboticlab.eu/ https://home.roboticlab.eu/_media/wiki/logo.png text/html 2026-03-01T12:00:18+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_1?rev=1772366418&do=diff Overall View on Computer Architecture: Processor, Memory, I/O, Buses The computers we use every day are all designed around the same general idea of cooperation among three base elements: processor, memory and peripheral devices. Their names represent their functions in the system: memory stores data and program code, the processor manipulates data by executing programs, and peripherals maintain contact with the user, the environment and other systems. To exchange information, these elements co… text/html 2026-03-29T14:47:47+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_2?rev=1774795667&do=diff Von Neumann vs Harvard Architectures, Mixed Architectures The classical architecture of computers uses a single address and a single data bus to connect the processor, memory and peripherals. This architecture is called the von Neumann or Princeton architecture, and we showed it in Fig. text/html 2026-02-27T12:24:14+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_3?rev=1772195054&do=diff CISC, RISC It is not only the whole computer that can have a different architecture. This also touches processors. There are two main internal processor architectures: CISC and RISC. CISC stands for Complex Instruction Set Computer, while RISC stands for Reduced Instruction Set Computer. The naming difference can be a little confusing because it treats the instruction set as complex or reduced. We can find CISC and RISC processors with a similar number of instructions implemented. The differenc… text/html 2026-01-10T18:11:26+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_4?rev=1768068686&do=diff Components of Processor: Registers, ALU, Bus Control, Instruction Decoder From our perspective, the processor is the electronic integrated circuit that controls other elements of the computer. Its main ability is to execute instructions. While we will go into details of the instruction set, you will see that some instructions perform calculations or process data, while others do not. This suggests that the processor comprises two main units. One of them is responsible for instruction execution,… text/html 2026-02-27T12:24:34+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_5?rev=1772195074&do=diff Processor Taxonomies, SISD, SIMD, MIMD, MISD, SIMT As we already know, the processor executes instructions that process data. We can consider two streams flowing through the processor. A stream of instructions which passes through the control unit, and a stream of data processed by the execution unit. In 1966, Michael Flynn proposed the taxonomies to define different processors' architectures. Flynn classification is based on the number of concurrent instruction (or control) streams and data st… text/html 2026-03-01T11:57:52+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_6?rev=1772366272&do=diff Memory, Types and Their Functions The computer cannot work without memory. The processor fetches instructions from memory, and data is stored there as well. In this chapter, we will discuss memory types, technologies and their properties. The overall view of computer memory can be represented by the memory hierarchy triangle shown in Fig. text/html 2026-03-01T11:59:10+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_7?rev=1772366350&do=diff Peripherals Peripherals or peripheral devices, also known as Input-Output (I/O) devices, enable the computer to remain in contact with the external environment or expand the computer's functionality. Peripheral devices enhance the computer's capability by making it possible to enter information into a computer for storage or processing and to deliver the processed data to a user, another computer, or a device controlled by the computer. Internal peripherals are connected directly to the compute… text/html 2026-04-01T11:00:39+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_8?rev=1775041239&do=diff Instruction Execution Process As we already mentioned, instructions are executed by the processor in a few steps. The literature describes three, four, or five stages of instruction execution. Everything depends on the level of detail one considers. The three-stage description says that there are fetch, decode and execute steps. The four-stage model says that there are fetch, decode, data read and execute steps, or fetch, decode, execute and store steps. The five-stage version adds both data re… text/html 2026-04-01T11:16:01+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_9?rev=1775042161&do=diff Modern Processors: Cache, Pipeline, Superscalar, Branch Prediction, Hyperthreading Modern processors have a highly complex design and include many units that primarily reduce software execution time. Cache Cache memory is a layer in the memory hierarchy that sits between main memory and processor registers. The main reason for introducing cache memory is that main memory, based on DRAM technology, is much slower than the processor, which is based on static technology. The cache exploits two … text/html 2026-03-01T12:14:15+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_10?rev=1772367255&do=diff Fundamentals of Addressing Modes Addressing Mode is the way in which the argument of an instruction is specified. The addressing mode defines a rule for interpreting the address field of the instruction before the operand is reached. Addressing mode is used in instructions that operate on data or change the program flow. text/html 2026-03-29T15:24:00+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_11?rev=1774797840&do=diff Fundamentals of Data Encoding, Big Endian, Little Endian The processor can work with different types of data. These include integers of different sizes, floating-point numbers, text, structures, and even single bits. All this data is stored in the memory as a single byte or multiple bytes. text/html 2026-01-10T18:21:13+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_12?rev=1768069273&do=diff Interrupt Controller, Interrupts An interrupt is a request to the processor to temporarily suspend the currently executing code in order to handle the event that caused the interrupt. If the request is accepted by the processor, it saves its state and executes an interrupt handler, also known as an interrupt service routine (ISR). Interrupts are usually signalled by peripheral devices in a situation when they have some data to process. Often, peripheral devices do not send an interrupt signal d… text/html 2026-03-29T15:00:14+00:00 Anonymous (anonymous@undisclosed.example.com) https://home.roboticlab.eu/en/multiasm/cs/chapter_3_13?rev=1774796414&do=diff DMA Direct memory access (DMA) is the mechanism for fast data transfer between peripherals and memory. In some implementations, it is also possible to transfer data between two peripherals or from memory to memory. DMA operates without processor activity. No software is executed during the DMA transfer. It must be supported by a processor and peripheral hardware, and a DMA controller must be present in the system. The controller plays a key role in transferring data.