Differences

This shows you the differences between two versions of the page.

--- en:multiasm:piot:chapter_4_3 [2026/01/19 14:59] – marcin
+++ en:multiasm:piot:chapter_4_3 [2026/01/19 15:08] (current) – marcin
@@ Line 13: / Line 13: @@
 Comparison Table: AVR Registers R0–R15 vs. R16–R31
-^ Feature                    ^ R0–R15                                                 ^ R16–R31                                                    ^
+^  Feature                     ^  R0–R15                                                            ^  R16–R31                                        ^
-| Instruction compatibility  | Cannot be used with immediate instructions (LDI, CPI, ORI, ANDI) | Fully compatible with immediate instructions |
+|  Instruction compatibility   |  Cannot be used with immediate instructions (LDI, CPI, ORI, ANDI)  |  Fully compatible with immediate instructions   |
-| Opcode encoding            | Not encodable in 4‑bit register fields                     | Encodable in all immediate‑type formats      |
+|  Opcode encoding             |  Not encodable in 4‑bit register fields                            |  Encodable in all immediate‑type formats        |
-| Typical compiler usage     | Less preferred; used for temporary or special roles        | Preferred for arithmetic and logic operations |
+|  Typical compiler usage      |  Less preferred; used for temporary or special roles               |  Preferred for arithmetic and logic operations  |
-| Special-purpose roles      | R0: scratch<br>R1: constant zero                           | R26–R31 used as X/Y/Z pointer registers      |
+|  Special-purpose roles       |  R0: scratch<br>R1: constant zero                                  |  R26–R31 used as X/Y/Z pointer registers        |
-| Pointer support            | No                                                         | Yes: X, Y, Z pointers                        |
+|  Pointer support             |  No                                                                |  Yes: X, Y, Z pointers                          |
-| Efficiency                 | Less efficient for immediate operations                    | More efficient due to shorter opcodes        |
+|  Efficiency                  |  Less efficient for immediate operations                           |  More efficient due to shorter opcodes          |
-| Multiplication involvement | R0/R1 used implicitly for results                          | Not used by multipliers                      |
+|  Multiplication involvement  |  R0/R1 used implicitly for results                                 |  Not used by multipliers                        |
-| Suitability in ASM         | Limited; avoid with immediates; R0/R1 have special rules   | Recommended for general ALU operations        |
+|  Suitability in ASM          |  Limited; avoid with immediates; R0/R1 have special rules          |  Recommended for general ALU operations         |
-| GCC policy                 | R1 must remain 0; R0 is volatile                           | Treated as normal general-purpose registers  |
+|  GCC policy                  |  R1 must remain 0; R0 is volatile                                  |  Treated as normal general-purpose registers    |
 <figure avr_registers>
-{{en:multiasm:piot:avr_register1.svg?800|AVR Registers}}
+{{en:multiasm:piot:avr_register1.svg?300|AVR Registers}}
 <caption>AVR Registers</caption>
 </figure>
@@ Line 35: / Line 35: @@
 <figure avr_registers>
-{{en:multiasm:piot:x_y_z_registers.svg?800|Extended registers}}
+{{en:multiasm:piot:x_y_z_registers.svg?400|Extended registers}}
 <caption>Etended Registers</caption>
 </figure>